mirror of https://github.com/YosysHQ/yosys.git
Add "write_smt2 -stbv"
This commit is contained in:
Clifford Wolf
parent
a9c3acf5a2
commit
7af9727f78
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@ -33,6 +33,7 @@ struct Smt2Worker
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SigMap sigmap;
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RTLIL::Module *module;
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bool bvmode, memmode, wiresmode, verbose, statebv;
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dict<IdString, int> &mod_stbv_width;
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int idcounter, statebv_width;
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std::vector<std::string> decls, trans, hier;
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@ -91,12 +92,10 @@ struct Smt2Worker
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decls.push_back(decl_str + "\n");
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}
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Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose) :
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ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode),
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wiresmode(wiresmode), verbose(verbose), idcounter(0)
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Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose, bool statebv, dict<IdString, int> &mod_stbv_width) :
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ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode), wiresmode(wiresmode),
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verbose(verbose), statebv(statebv), mod_stbv_width(mod_stbv_width), idcounter(0), statebv_width(0)
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{
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statebv_width = 0;
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statebv = bvmode && !memmode && false; // FIXME
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makebits(stringf("%s_is", get_id(module)));
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for (auto cell : module->cells())
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@ -537,30 +536,80 @@ struct Smt2Worker
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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int rd_ports = cell->getParam("\\RD_PORTS").as_int();
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int wr_ports = cell->getParam("\\WR_PORTS").as_int();
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decls.push_back(stringf("(declare-fun |%s#%d#0| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
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get_id(module), arrayid, get_id(module), abits, width, get_id(cell)));
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decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d\n", get_id(cell), abits, width, rd_ports, wr_ports));
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decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d\n", get_id(cell), abits, width, rd_ports));
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decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s#%d#0| state))\n",
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get_id(module), get_id(cell), get_id(module), abits, width, get_id(module), arrayid));
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for (int i = 0; i < rd_ports; i++)
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if (statebv)
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{
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SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
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SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
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std::string addr = get_bv(addr_sig);
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int mem_size = cell->getParam("\\SIZE").as_int();
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int mem_offset = cell->getParam("\\OFFSET").as_int();
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if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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makebits(stringf("%s#%d#0", get_id(module), arrayid), width*mem_size, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d#0| state))\n",
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get_id(module), get_id(cell), get_id(module), width*mem_size, get_id(module), arrayid));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) %s)) ; %s\n",
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get_id(module), idcounter, get_id(module), width, get_id(module), arrayid, addr.c_str(), log_signal(data_sig)));
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register_bv(data_sig, idcounter++);
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for (int i = 0; i < rd_ports; i++)
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{
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SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
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SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
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std::string addr = get_bv(addr_sig);
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if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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std::string read_expr = "#b";
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for (int k = 0; k < width; k++)
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read_expr += "0";
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for (int k = 0; k < mem_size; k++)
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read_expr = stringf("(ite (= (|%s_m:%d %s| state) #b%s) ((_ extract %d %d) (|%s#%d#0| state))\n %s)",
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get_id(module), i, get_id(cell), Const(k+mem_offset, abits).as_string().c_str(),
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width*(k+1)-1, width*k, get_id(module), arrayid, read_expr.c_str());
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
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get_id(module), idcounter, get_id(module), width, read_expr.c_str(), log_signal(data_sig)));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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}
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}
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else
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{
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decls.push_back(stringf("(declare-fun |%s#%d#0| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
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get_id(module), arrayid, get_id(module), abits, width, get_id(cell)));
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decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s#%d#0| state))\n",
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get_id(module), get_id(cell), get_id(module), abits, width, get_id(module), arrayid));
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for (int i = 0; i < rd_ports; i++)
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{
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SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
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SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
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std::string addr = get_bv(addr_sig);
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if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) (|%s_m:%d %s| state))) ; %s\n",
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get_id(module), idcounter, get_id(module), width, get_id(module), arrayid, get_id(module), i, get_id(cell), log_signal(data_sig)));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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}
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}
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registers.insert(cell);
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@ -598,9 +647,11 @@ struct Smt2Worker
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}
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}
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// FIXME (statebv)
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decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
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get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
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if (statebv)
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makebits(stringf("%s_h %s", get_id(module), get_id(cell->name)), mod_stbv_width.at(cell->type));
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else
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decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
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get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
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hiercells.insert(cell);
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hiercells_queue.insert(cell);
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@ -741,21 +792,82 @@ struct Smt2Worker
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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int rd_ports = cell->getParam("\\RD_PORTS").as_int();
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int wr_ports = cell->getParam("\\WR_PORTS").as_int();
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for (int i = 0; i < wr_ports; i++)
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if (statebv)
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{
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std::string addr = get_bv(cell->getPort("\\WR_ADDR").extract(abits*i, abits));
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std::string data = get_bv(cell->getPort("\\WR_DATA").extract(width*i, width));
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std::string mask = get_bv(cell->getPort("\\WR_EN").extract(width*i, width));
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int mem_size = cell->getParam("\\SIZE").as_int();
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int mem_offset = cell->getParam("\\OFFSET").as_int();
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data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
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data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
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for (int i = 0; i < wr_ports; i++)
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{
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SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
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SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
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SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
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decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
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"(store (|%s#%d#%d| state) %s %s)) ; %s\n",
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get_id(module), arrayid, i+1, get_id(module), abits, width,
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get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
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std::string addr = get_bv(addr_sig);
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std::string data = get_bv(data_sig);
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std::string mask = get_bv(mask_sig);
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
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std::string data_expr;
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for (int k = mem_size-1; k >= 0; k--) {
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std::string new_data = stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
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data.c_str(), mask.c_str(), width*(k+1)-1, width*k, get_id(module), arrayid, i, mask.c_str());
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data_expr += stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
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addr.c_str(), Const(k+mem_offset, abits).as_string().c_str(), new_data.c_str(),
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width*(k+1)-1, width*k, get_id(module), arrayid, i);
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}
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decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
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get_id(module), arrayid, i+1, get_id(module), width*mem_size, data_expr.c_str(), get_id(cell)));
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}
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}
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else
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{
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for (int i = 0; i < wr_ports; i++)
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{
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SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
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SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
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SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
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std::string addr = get_bv(addr_sig);
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std::string data = get_bv(data_sig);
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std::string mask = get_bv(mask_sig);
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
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data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
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data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
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decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
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"(store (|%s#%d#%d| state) %s %s)) ; %s\n",
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get_id(module), arrayid, i+1, get_id(module), abits, width,
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get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
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}
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}
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std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
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@ -777,10 +889,14 @@ struct Smt2Worker
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if (bit == State::S0 || bit == State::S1)
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gen_init_constr = true;
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if (gen_init_constr) {
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init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
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get_id(module), arrayid, Const(i, abits).as_string().c_str(),
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initword.as_string().c_str(), get_id(cell), i));
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if (gen_init_constr)
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{
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if (statebv)
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/* FIXME */;
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else
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init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
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get_id(module), arrayid, Const(i, abits).as_string().c_str(),
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initword.as_string().c_str(), get_id(cell), i));
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}
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}
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}
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@ -876,9 +992,10 @@ struct Smt2Worker
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{
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f << stringf("; yosys-smt2-module %s\n", get_id(module));
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if (statebv)
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if (statebv) {
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f << stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module), statebv_width);
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else
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mod_stbv_width[module->name] = statebv_width;
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} else
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f << stringf("(declare-sort |%s_s| 0)\n", get_id(module));
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for (auto it : decls)
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@ -951,6 +1068,11 @@ struct Smt2Backend : public Backend {
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log(" -verbose\n");
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log(" this will print the recursive walk used to export the modules.\n");
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log("\n");
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log(" -stbv\n");
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log(" Use a BitVec sort to represent a state instead of an uninterpreted\n");
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log(" sort. As a side-effect this will prevent use of arrays to model\n");
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log(" memories.\n");
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log("\n");
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log(" -nobv\n");
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log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
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log(" option multi-bit wires are represented using the BitVec sort and\n");
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@ -1024,7 +1146,7 @@ struct Smt2Backend : public Backend {
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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std::ifstream template_f;
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bool bvmode = true, memmode = true, wiresmode = false, verbose = false;
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bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false;
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log_header(design, "Executing SMT2 backend.\n");
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@ -1041,6 +1163,10 @@ struct Smt2Backend : public Backend {
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log_warning("Options -bv and -mem are now the default. Support for -bv and -mem will be removed in the future.\n");
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continue;
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}
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if (args[argidx] == "-stbv") {
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statebv = true;
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continue;
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}
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if (args[argidx] == "-nobv") {
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bvmode = false;
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memmode = false;
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@ -1082,6 +1208,9 @@ struct Smt2Backend : public Backend {
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if (!memmode)
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*f << stringf("; yosys-smt2-nomem\n");
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if (statebv)
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*f << stringf("; yosys-smt2-stbv\n");
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std::vector<RTLIL::Module*> sorted_modules;
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// extract module dependencies
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@ -1111,6 +1240,7 @@ struct Smt2Backend : public Backend {
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module_deps.erase(sorted_modules.at(sorted_modules_idx++));
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}
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dict<IdString, int> mod_stbv_width;
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Module *topmod = design->top_module();
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std::string topmod_id;
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@ -1121,7 +1251,7 @@ struct Smt2Backend : public Backend {
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log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
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Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose);
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Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose, statebv, mod_stbv_width);
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worker.run();
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worker.write(*f);
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|
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@ -613,12 +613,12 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
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mems = sorted(smt.hiermems(topmod))
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for mempath in mems:
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abits, width, ports = smt.mem_info(topmod, mempath)
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abits, width, rports, wports = smt.mem_info(topmod, mempath)
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mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
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addr_expr_list = list()
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||||
for i in range(steps_start, steps_stop):
|
||||
for j in range(ports):
|
||||
for j in range(rports):
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||||
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
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||||
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||||
addr_list = set()
|
||||
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|
@ -674,12 +674,12 @@ def write_constr_trace(steps_start, steps_stop, index):
|
|||
|
||||
mems = sorted(smt.hiermems(topmod))
|
||||
for mempath in mems:
|
||||
abits, width, ports = smt.mem_info(topmod, mempath)
|
||||
abits, width, rports, wports = smt.mem_info(topmod, mempath)
|
||||
mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
|
||||
|
||||
addr_expr_list = list()
|
||||
for i in range(steps_start, steps_stop):
|
||||
for j in range(ports):
|
||||
for j in range(rports):
|
||||
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
|
||||
|
||||
addr_list = set((smt.bv2int(val) for val in smt.get_list(addr_expr_list)))
|
||||
|
|
|
|||
|
|
@ -328,7 +328,7 @@ class SmtIo:
|
|||
self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
|
||||
|
||||
if fields[1] == "yosys-smt2-memory":
|
||||
self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]))
|
||||
self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]), int(fields[6]))
|
||||
|
||||
if fields[1] == "yosys-smt2-wire":
|
||||
self.modinfo[self.curmod].wires.add(fields[2])
|
||||
|
|
|
|||
Loading…
Reference in New Issue