mirror of https://github.com/YosysHQ/yosys.git
Fixed another bug in write_blif handling of $lut cells
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@ -220,7 +220,7 @@ struct BlifDumper
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auto &inputs = cell->getPort("\\A");
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auto width = cell->parameters.at("\\WIDTH").as_int();
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log_assert(inputs.size() == width);
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for (int i = 0; i < inputs.size(); i++) {
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for (int i = width-1; i >= 0; i--) {
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f << stringf(" %s", cstr(inputs.extract(i, 1)));
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}
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auto &output = cell->getPort("\\Y");
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