mirror of https://github.com/YosysHQ/yosys.git
Improved smtbmc vcd generation performance
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parent
dfcd30ea86
commit
de8ee412c3
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@ -111,14 +111,16 @@ def write_vcd_model(steps):
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print("%s Writing model to VCD file." % smt.timestamp())
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vcd = mkvcd(open(vcdfile, "w"))
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for netpath in sorted(smt.hiernets(topmod)):
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width = len(smt.get_net_bin(topmod, netpath, "s0"))
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vcd.add_net([topmod] + netpath, width)
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vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
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for i in range(steps):
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vcd.set_time(i)
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for netpath in sorted(smt.hiernets(topmod)):
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vcd.set_net([topmod] + netpath, smt.get_net_bin(topmod, netpath, "s%d" % i))
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path_list = sorted(smt.hiernets(topmod))
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value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
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for path, value in zip(path_list, value_list):
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vcd.set_net([topmod] + path, value)
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vcd.set_time(steps)
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@ -157,7 +157,7 @@ class smtio:
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print("< %s" % line)
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if count_brackets == 0:
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break
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if not self.p.poll():
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if self.p.poll():
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print("SMT Solver terminated unexpectedly: %s" % "".join(stmt))
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sys.exit(1)
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@ -297,33 +297,51 @@ class smtio:
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self.write("(get-value (%s))" % (expr))
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return self.parse(self.read())[0][1]
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def get_net(self, mod_name, net_path, state_name):
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def mkexpr(mod, base, path):
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if len(path) == 1:
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assert mod in self.modinfo
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assert path[0] in self.modinfo[mod].wsize
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return "(|%s_n %s| %s)" % (mod, path[0], base)
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def get_list(self, expr_list):
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self.write("(get-value (%s))" % " ".join(expr_list))
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return [n[1] for n in self.parse(self.read())]
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def net_expr(self, mod, base, path):
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if len(path) == 1:
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assert mod in self.modinfo
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assert path[0] in self.modinfo[mod].cells
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assert path[0] in self.modinfo[mod].wsize
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return "(|%s_n %s| %s)" % (mod, path[0], base)
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nextmod = self.modinfo[mod].cells[path[0]]
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nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
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return mkexpr(nextmod, nextbase, path[1:])
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assert mod in self.modinfo
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assert path[0] in self.modinfo[mod].cells
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return self.get(mkexpr(mod_name, state_name, net_path))
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nextmod = self.modinfo[mod].cells[path[0]]
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nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
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return self.net_expr(nextmod, nextbase, path[1:])
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def get_net_bool(self, mod_name, net_path, state_name):
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v = self.get_net(mod_name, net_path, state_name)
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assert v in ["true", "false"]
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return 1 if v == "true" else 0
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def net_width(self, mod, net_path):
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for i in range(len(net_path)-1):
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assert mod in self.modinfo
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assert net_path[i] in self.modinfo[mod].cells
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mod = self.modinfo[mod].cells[net_path[i]]
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assert mod in self.modinfo
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assert net_path[-1] in self.modinfo[mod].wsize
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return self.modinfo[mod].wsize[net_path[-1]]
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def get_net(self, mod_name, net_path, state_name):
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return self.get(self.net_expr(mod_name, state_name, net_path))
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def get_net_list(self, mod_name, net_path_list, state_name):
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return self.get_list([self.net_expr(mod_name, state_name, n) for n in net_path_list])
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def get_net_hex(self, mod_name, net_path, state_name):
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return self.bv2hex(self.get_net(mod_name, net_path, state_name))
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def get_net_hex_list(self, mod_name, net_path_list, state_name):
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return [self.bv2hex(v) for v in self.get_net_list(mod_name, net_path_list, state_name)]
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def get_net_bin(self, mod_name, net_path, state_name):
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return self.bv2bin(self.get_net(mod_name, net_path, state_name))
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def get_net_bin_list(self, mod_name, net_path_list, state_name):
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return [self.bv2bin(v) for v in self.get_net_list(mod_name, net_path_list, state_name)]
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def wait(self):
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self.p.wait()
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