mirror of https://github.com/YosysHQ/yosys.git
Added edif backend (still under construction)
This commit is contained in:
Clifford Wolf
parent
8409956c0c
commit
aba8639a3f
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OBJS += backends/edif/edif.o
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@ -0,0 +1,199 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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#include <assert.h>
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struct EdifBackend : public Backend {
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EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_edif [options] [filename]\n");
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log("\n");
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log("Write the current design to an EDIF netlist file.\n");
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log("\n");
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log(" -top top_module\n");
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log(" set the specified module as design top module\n");
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log("\n");
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log("FIXME: This backend in under construction!\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing EDIF backend.\n");
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std::string top_module_name;
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std::map<std::string, std::set<std::string>> lib_cell_ports;
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CellTypes ct(design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module_name = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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for (auto module_it : design->modules)
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{
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RTLIL::Module *module = module_it.second;
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if ((module->attributes.count("\\placeholder") > 0) > 0)
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continue;
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if (top_module_name.empty())
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top_module_name = module->name;
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if (module->processes.size() != 0)
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log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
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if (module->memories.size() != 0)
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log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
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for (auto cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (!design->modules.count(cell->type) || design->modules.at(cell->type)->attributes.count("\\placeholder")) {
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lib_cell_ports[cell->type];
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for (auto p : cell->connections) {
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if (p.second.width > 1)
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log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
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RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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lib_cell_ports[cell->type].insert(p.first);
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}
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}
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}
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}
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if (top_module_name.empty())
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log_error("No module found in design!\n");
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fprintf(f, "(edif %s\n", RTLIL::id2cstr(top_module_name));
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fprintf(f, " (edifVersion 2 0 0)\n");
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fprintf(f, " (edifLevel 0)\n");
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fprintf(f, " (keywordMap (keywordLevel 0))\n");
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fprintf(f, " (external LIB\n");
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fprintf(f, " (edifLevel 0)\n");
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fprintf(f, " (technology (numberDefinition))\n");
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for (auto &cell_it : lib_cell_ports) {
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fprintf(f, " (cell %s\n", RTLIL::id2cstr(cell_it.first));
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fprintf(f, " (cellType GENERIC)\n");
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fprintf(f, " (view VIEW_NETLIST\n");
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fprintf(f, " (viewType NETLIST)\n");
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fprintf(f, " (interface\n");
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for (auto &port_it : cell_it.second) {
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const char *dir = "INOUT";
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if (ct.cell_known(cell_it.first)) {
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if (!ct.cell_output(cell_it.first, port_it))
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dir = "INPUT";
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else if (!ct.cell_input(cell_it.first, port_it))
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dir = "OUTPUT";
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}
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fprintf(f, " (port %s (direction %s))\n", RTLIL::id2cstr(port_it), dir);
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}
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fprintf(f, " )\n");
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fprintf(f, " )\n");
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fprintf(f, " )\n");
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}
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fprintf(f, " )\n");
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fprintf(f, " (library DESIGN\n");
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fprintf(f, " (edifLevel 0)\n");
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fprintf(f, " (technology (numberDefinition))\n");
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for (auto module_it : design->modules)
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{
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RTLIL::Module *module = module_it.second;
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if ((module->attributes.count("\\placeholder") > 0) > 0)
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continue;
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SigMap sigmap(module);
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std::map<RTLIL::SigSpec, std::set<std::string>> net_join_db;
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fprintf(f, " (cell %s\n", RTLIL::id2cstr(module->name));
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fprintf(f, " (cellType GENERIC)\n");
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fprintf(f, " (view VIEW_NETLIST\n");
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fprintf(f, " (viewType NETLIST)\n");
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fprintf(f, " (interface\n");
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for (auto &wire_it : module->wires) {
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_id == 0)
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continue;
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const char *dir = "INOUT";
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if (!wire->port_output)
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dir = "INPUT";
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else if (!wire->port_input)
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dir = "OUTPUT";
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for (int i = 0; i < wire->width; i++) {
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std::string portname = wire->width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(wire->name),
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i+wire->start_offset) : RTLIL::id2cstr(wire->name);
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fprintf(f, " (port %s (direction %s))\n", portname.c_str(), dir);
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RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
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net_join_db[sig].insert(stringf("(portRef %s)", portname.c_str()));
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}
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}
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fprintf(f, " )\n");
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fprintf(f, " (contents\n");
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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fprintf(f, " (instance %s (viewRef VIEW_NETLIST (cellRef %s%s)))\n",
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RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type),
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lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
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for (auto &p : cell->connections) {
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RTLIL::SigSpec sig = sigmap(p.second);
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sig.expand();
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for (int i = 0; i < sig.width; i++) {
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RTLIL::SigSpec sigbit(sig.chunks.at(i));
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std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first);
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net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", portname.c_str(), RTLIL::id2cstr(cell->name)));
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}
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}
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}
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for (auto &it : net_join_db) {
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std::string netname = log_signal(it.first);
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for (size_t i = 0; i < netname.size(); i++)
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if (netname[i] == ' ' || netname[i] == '\\')
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netname.erase(netname.begin() + i--);
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fprintf(f, " (net %s (joined\n", netname.c_str());
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for (auto &ref : it.second)
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fprintf(f, " %s\n", ref.c_str());
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fprintf(f, " ))\n");
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}
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fprintf(f, " )\n");
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fprintf(f, " )\n");
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fprintf(f, " )\n");
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}
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fprintf(f, " )\n");
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fprintf(f, " (design %s\n", RTLIL::id2cstr(top_module_name));
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fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", RTLIL::id2cstr(top_module_name));
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fprintf(f, " )\n");
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fprintf(f, ")\n");
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}
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} EdifBackend;
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