mirror of https://github.com/YosysHQ/yosys.git
More cleanup
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7328775584
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@ -50,7 +50,6 @@ struct XAigerWriter
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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@ -305,32 +304,24 @@ struct XAigerWriter
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}
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if (bmode) {
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aig_b++;
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//aig_b++;
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aig_outputs.push_back(0);
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
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{
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int aig_obc = aig_o + aig_b + aig_c;
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int aig_obcj = aig_obc + aig_j;
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int aig_obcjf = aig_obcj + aig_f;
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int aig_obc = aig_o;
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int aig_obcj = aig_obc;
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int aig_obcjf = aig_obcj;
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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log_assert(aig_l == GetSize(aig_latchinit));
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log_assert(aig_obcjf == GetSize(aig_outputs));
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if (miter_mode) {
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if (aig_b || aig_c || aig_j || aig_f)
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log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
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f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
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} else {
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f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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if (aig_b || aig_c || aig_j || aig_f)
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f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
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f << stringf("\n");
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}
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f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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f << stringf("\n");
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if (ascii_mode)
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{
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