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yosys-smtbmc meminit support

This commit is contained in:
Clifford Wolf 2016-09-08 11:16:12 +02:00
parent 209a3d9ffc
commit 14bfd3c5c1
4 changed files with 52 additions and 5 deletions
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26
backends/smt2/smt2.cc
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@ -736,6 +736,26 @@ struct Smt2Worker
std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid);
trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell)));
Const init_data = cell->getParam("\\INIT");
int memsize = cell->getParam("\\SIZE").as_int();
for (int i = 0; i < memsize; i++)
{
if (GetSize(init_data) < i*width)
break;
Const initword = init_data.extract(i*width, width, State::Sx);
bool gen_init_constr = false;
for (auto bit : initword.bits)
if (bit == State::S0 || bit == State::S1)
gen_init_constr = true;
init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
get_id(module), arrayid, Const(i, abits).as_string().c_str(),
initword.as_string().c_str(), get_id(cell), i));
}
}
}
}
@ -864,8 +884,8 @@ struct Smt2Backend : public Backend {
log(" this will print the recursive walk used to export the modules.\n");
log("\n");
log(" -nobv\n");
log(" disable support for BitVec (FixedSizeBitVectors theory). with this\n");
log(" option set multi-bit wires are represented using the BitVec sort and\n");
log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
log(" option multi-bit wires are represented using the BitVec sort and\n");
log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
log("\n");
log(" -nomem\n");
@ -878,7 +898,7 @@ struct Smt2Backend : public Backend {
log("\n");
log(" -wires\n");
log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
log(" registers, and wires with the 'keep' attribute set are exported.\n");
log(" registers, and wires with the 'keep' attribute are exported.\n");
log("\n");
log(" -tpl <template_file>\n");
log(" use the given template file. the line containing only the token '%%%%'\n");

2
examples/smtbmc/.gitignore vendored
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@ -18,3 +18,5 @@ demo5.vcd
demo5.yslog
demo6.smt2
demo6.yslog
demo7.smt2
demo7.yslog

11
examples/smtbmc/Makefile
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@ -1,5 +1,5 @@
all: demo1 demo2 demo3 demo4 demo5 demo6
all: demo1 demo2 demo3 demo4 demo5 demo6 demo7
demo1: demo1.smt2
yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
@ -22,6 +22,9 @@ demo5: demo5.smt2
demo6: demo6.smt2
yosys-smtbmc -t 1 demo6.smt2
demo7: demo7.smt2
yosys-smtbmc -t 10 demo7.smt2
demo1.smt2: demo1.v
yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2'
@ -40,6 +43,9 @@ demo5.smt2: demo5.v
demo6.smt2: demo6.v
yosys -ql demo6.yslog -p 'read_verilog demo6.v; prep -top demo6 -nordff; assertpmux; opt -keepdc -fast; write_smt2 -wires demo6.smt2'
demo7.smt2: demo7.v
yosys -ql demo7.yslog -p 'read_verilog -formal demo7.v; prep -top demo7 -nordff; write_smt2 -wires demo7.smt2'
clean:
rm -f demo1.yslog demo1.smt2 demo1.vcd
rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
@ -47,6 +53,7 @@ clean:
rm -f demo4.yslog demo4.smt2 demo4.vcd
rm -f demo5.yslog demo5.smt2 demo5.vcd
rm -f demo6.yslog demo6.smt2
rm -f demo7.yslog demo7.smt2
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 clean
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 clean

18
examples/smtbmc/demo7.v Normal file
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@ -0,0 +1,18 @@
// Demo for memory initialization
module demo7 (input [2:0] addr);
reg [15:0] memory [0:7];
initial begin
memory[0] = 1331;
memory[1] = 1331 + 1;
memory[2] = 1331 + 2;
memory[3] = 1331 + 4;
memory[4] = 1331 + 8;
memory[5] = 1331 + 16;
memory[6] = 1331 + 32;
memory[7] = 1331 + 64;
end
assert property (1000 < memory[addr] && memory[addr] < 2000);
endmodule