mirror of https://github.com/YosysHQ/yosys.git
Improve (and fix for stbv mode) SMT2 memory API
This commit is contained in:
Clifford Wolf
parent
38bf458037
commit
fd1cc0c73d
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@ -560,7 +560,7 @@ struct Smt2Worker
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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std::string read_expr = "#b";
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@ -568,14 +568,14 @@ struct Smt2Worker
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read_expr += "0";
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for (int k = 0; k < mem_size; k++)
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read_expr = stringf("(ite (= (|%s_m:%d %s| state) #b%s) ((_ extract %d %d) (|%s#%d#0| state))\n %s)",
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read_expr = stringf("(ite (= (|%s_m:R%dA %s| state) #b%s) ((_ extract %d %d) (|%s#%d#0| state))\n %s)",
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get_id(module), i, get_id(cell), Const(k+mem_offset, abits).as_string().c_str(),
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width*(k+1)-1, width*k, get_id(module), arrayid, read_expr.c_str());
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
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get_id(module), idcounter, get_id(module), width, read_expr.c_str(), log_signal(data_sig)));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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@ -599,13 +599,13 @@ struct Smt2Worker
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log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) (|%s_m:%d %s| state))) ; %s\n",
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decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) (|%s_m:R%dA %s| state))) ; %s\n",
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get_id(module), idcounter, get_id(module), width, get_id(module), arrayid, get_id(module), i, get_id(cell), log_signal(data_sig)));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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decls.push_back(stringf("(define-fun |%s_m:R%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
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get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
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register_bv(data_sig, idcounter++);
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@ -792,7 +792,6 @@ struct Smt2Worker
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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int rd_ports = cell->getParam("\\RD_PORTS").as_int();
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int wr_ports = cell->getParam("\\WR_PORTS").as_int();
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if (statebv)
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@ -810,17 +809,17 @@ struct Smt2Worker
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std::string data = get_bv(data_sig);
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std::string mask = get_bv(mask_sig);
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
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std::string data_expr;
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@ -848,17 +847,17 @@ struct Smt2Worker
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std::string data = get_bv(data_sig);
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std::string mask = get_bv(mask_sig);
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decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
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addr = stringf("(|%s_m:W%dA %s| state)", get_id(module), i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
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data = stringf("(|%s_m:W%dD %s| state)", get_id(module), i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
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decls.push_back(stringf("(define-fun |%s_m:W%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
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get_id(module), i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
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mask = stringf("(|%s_m:W%dM %s| state)", get_id(module), i, get_id(cell));
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data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
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data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
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@ -614,24 +614,26 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
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mems = sorted(smt.hiermems(topmod))
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for mempath in mems:
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abits, width, rports, wports = smt.mem_info(topmod, mempath)
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mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
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addr_expr_list = list()
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data_expr_list = list()
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for i in range(steps_start, steps_stop):
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for j in range(rports):
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addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
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addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
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data_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
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addr_list = set()
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for val in smt.get_list(addr_expr_list):
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addr_list.add(smt.bv2int(val))
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addr_list = smt.get_list(addr_expr_list)
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data_list = smt.get_list(data_expr_list)
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expr_list = list()
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for i in addr_list:
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expr_list.append("(select %s #b%s)" % (mem, format(i, "0%db" % abits)))
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addr_data = dict()
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for addr, data in zip(addr_list, data_list):
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addr = smt.bv2bin(addr)
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data = smt.bv2bin(data)
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if addr not in addr_data:
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addr_data[addr] = data
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for i, val in zip(addr_list, smt.get_list(expr_list)):
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val = smt.bv2bin(val)
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print(" UUT.%s[%d] = %d'b%s;" % (".".join(mempath), i, len(val), val), file=f)
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for addr, data in addr_data.items():
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print(" UUT.%s[%d'b%s] = %d'b%s;" % (".".join(mempath), len(addr), addr, len(data), data), file=f)
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for i in range(steps_start, steps_stop):
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pi_names = [[name] for name, _ in primary_inputs if name not in clock_inputs]
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@ -675,21 +677,24 @@ def write_constr_trace(steps_start, steps_stop, index):
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mems = sorted(smt.hiermems(topmod))
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for mempath in mems:
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abits, width, rports, wports = smt.mem_info(topmod, mempath)
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mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
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addr_expr_list = list()
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data_expr_list = list()
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for i in range(steps_start, steps_stop):
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for j in range(rports):
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addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
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addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
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data_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
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addr_list = set((smt.bv2int(val) for val in smt.get_list(addr_expr_list)))
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addr_list = smt.get_list(addr_expr_list)
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data_list = smt.get_list(data_expr_list)
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expr_list = list()
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for i in addr_list:
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expr_list.append("(select %s #b%s)" % (mem, format(i, "0%db" % abits)))
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addr_data = dict()
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for addr, data in zip(addr_list, data_list):
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if addr not in addr_data:
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addr_data[addr] = data
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for i, val in zip(addr_list, smt.get_list(expr_list)):
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print("assume (= (select [%s] #b%s) %s)" % (".".join(mempath), format(i, "0%db" % abits), val), file=f)
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for addr, data in addr_data.items():
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print("assume (= (select [%s] %s) %s)" % (".".join(mempath), addr, data), file=f)
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for k in range(steps_start, steps_stop):
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print("", file=f)
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@ -596,20 +596,20 @@ class SmtIo:
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if mem_path[-1] not in self.modinfo[mod].memories: return False
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return True
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def mem_expr(self, mod, base, path, portidx=None, infomode=False):
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def mem_expr(self, mod, base, path, port=None, infomode=False):
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if len(path) == 1:
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assert mod in self.modinfo
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assert path[0] in self.modinfo[mod].memories
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if infomode:
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return self.modinfo[mod].memories[path[0]]
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return "(|%s_m%s %s| %s)" % (mod, "" if portidx is None else ":%d" % portidx, path[0], base)
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return "(|%s_m%s %s| %s)" % (mod, "" if port is None else ":%s" % port, path[0], base)
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assert mod in self.modinfo
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assert path[0] in self.modinfo[mod].cells
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nextmod = self.modinfo[mod].cells[path[0]]
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nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
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return self.mem_expr(nextmod, nextbase, path[1:], portidx=portidx, infomode=infomode)
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return self.mem_expr(nextmod, nextbase, path[1:], port=port, infomode=infomode)
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def mem_info(self, mod, path):
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return self.mem_expr(mod, "", path, infomode=True)
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