mirror of https://github.com/YosysHQ/yosys.git
Improvements in cellaigs.cc and "json -aig"
This commit is contained in:
Clifford Wolf
parent
1ae360cf72
commit
3a6abc9bf6
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@ -216,11 +216,11 @@ struct JsonWriter
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if (!first_model)
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f << stringf(",\n");
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f << stringf(" \"%s\": [\n", aig.name.c_str());
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bool first_node = true;
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int node_idx = 0;
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for (auto &node : aig.nodes) {
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if (!first_node)
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if (node_idx != 0)
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f << stringf(",\n");
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f << stringf(" [ ");
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f << stringf(" /* %3d */ [ ", node_idx);
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if (node.portbit >= 0)
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f << stringf("\"%sport\", \"%s\", %d", node.inverter ? "n" : "",
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log_id(node.portname), node.portbit);
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@ -231,7 +231,7 @@ struct JsonWriter
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for (auto &op : node.outports)
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f << stringf(", \"%s\", %d", log_id(op.first), op.second);
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f << stringf(" ]");
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first_node = false;
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node_idx++;
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}
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f << stringf("\n ]");
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first_model = false;
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@ -253,7 +253,7 @@ struct JsonBackend : public Backend {
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log("Write a JSON netlist of the current design.\n");
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log("\n");
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log(" -aig\n");
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log(" also include AIG models for the different gate types\n");
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log(" include AIG models for the different gate types\n");
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log("\n");
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log("\n");
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log("The general syntax of the JSON output created by this command is as follows:\n");
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@ -274,7 +274,10 @@ struct JsonBackend : public Backend {
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log(" ...\n");
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log(" }\n");
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log(" }\n");
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log(" }\n");
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log(" },\n");
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log(" \"models\": {\n");
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log(" ...\n");
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log(" },\n");
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log(" }\n");
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log("\n");
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log("Where <port_details> is:\n");
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@ -387,6 +390,60 @@ struct JsonBackend : public Backend {
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log(" }\n");
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log(" }\n");
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log("\n");
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log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
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log("\n");
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log(" \"models\": {\n");
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log(" <model_name>: [\n");
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log(" /* 0 */ [ <node-spec> ],\n");
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log(" /* 1 */ [ <node-spec> ],\n");
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log(" /* 2 */ [ <node-spec> ],\n");
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log(" ...\n");
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log(" ],\n");
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log(" ...\n");
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log(" },\n");
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log("\n");
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log("The following node-types may be used:\n");
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log("\n");
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log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
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log(" - the value of the specified input port bit\n");
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log("\n");
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log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
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log(" - the inverted value of the specified input port bit\n");
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log("\n");
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log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
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log(" - the ANDed value of the speciefied nodes\n");
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log("\n");
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log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
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log(" - the inverted ANDed value of the speciefied nodes\n");
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log("\n");
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log(" [ \"true\", <out-list> ]\n");
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log(" - the constant value 1\n");
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log("\n");
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log(" [ \"false\", <out-list> ]\n");
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log(" - the constant value 0\n");
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log("\n");
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log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
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log("are referenced by \"and\" and \"nand\" nodes.\n");
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log("\n");
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log("The optional <out-list> at the end of a node specification is a list of\n");
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log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
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log("\n");
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log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
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log("inferred by the following code:\n");
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log("\n");
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log(" module test(input [2:0] in, output [2:0] out);\n");
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log(" assign in = &out;\n");
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log(" endmodule\n");
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log("\n");
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log(" \"$reduce_and:3U:3\": [\n");
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log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
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log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
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log(" /* 2 */ [ \"and\", 0, 1 ],\n");
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log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
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log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
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log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
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log(" ]\n");
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log("\n");
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log("Future version of Yosys might add support for additional fields in the JSON\n");
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log("format. A program processing this format must ignore all unkown fields.\n");
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log("\n");
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@ -112,6 +112,14 @@ struct AigMaker
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return node2index(node);
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}
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vector<int> inport_vec(IdString portname, int width)
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{
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vector<int> vec;
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for (int i = 0; i < width; i++)
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vec.push_back(inport(portname, i));
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return vec;
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}
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int not_inport(IdString portname, int portbit = 0)
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{
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return inport(portname, portbit, true);
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@ -128,7 +136,7 @@ struct AigMaker
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int and_gate(int A, int B, bool inverter = false)
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{
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if (A == B)
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return A;
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return inverter ? not_gate(A) : A;
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const AigNode &nA = aig_indices[A];
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const AigNode &nB = aig_indices[B];
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@ -199,11 +207,39 @@ struct AigMaker
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return or_gate(and_gate(A, not_gate(S)), and_gate(B, S));
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}
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vector<int> adder(const vector<int> &A, const vector<int> &B, int carry, vector<int> *X = nullptr, vector<int> *CO = nullptr)
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{
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vector<int> Y(GetSize(A));
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log_assert(GetSize(A) == GetSize(B));
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for (int i = 0; i < GetSize(A); i++) {
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Y[i] = xor_gate(xor_gate(A[i], B[i]), carry);
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carry = or_gate(and_gate(A[i], B[i]), and_gate(or_gate(A[i], B[i]), carry));
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if (X != nullptr)
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X->at(i) = xor_gate(A[i], B[i]);
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if (CO != nullptr)
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CO->at(i) = carry;
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}
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return Y;
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}
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void outport(int node, IdString portname, int portbit = 0)
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{
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if (portbit < GetSize(cell->getPort(portname)))
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aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
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}
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void outport_bool(int node, IdString portname)
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{
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outport(node, portname);
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for (int i = 1; i < GetSize(cell->getPort(portname)); i++)
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outport(bool_node(false), portname, i);
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}
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void outport_vec(const vector<int> &vec, IdString portname)
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{
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for (int i = 0; i < GetSize(vec); i++)
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outport(vec.at(i), portname, i);
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}
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};
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Aig::Aig(Cell *cell)
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@ -214,15 +250,41 @@ Aig::Aig(Cell *cell)
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AigMaker mk(this, cell);
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name = cell->type.str();
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string mkname_last;
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bool mkname_a_signed = false;
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bool mkname_b_signed = false;
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bool mkname_is_signed = false;
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cell->parameters.sort();
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for (auto p : cell->parameters)
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name += stringf(":%d", p.second.as_int());
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{
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if (p.first == "\\A_WIDTH" && mkname_a_signed) {
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name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
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} else if (p.first == "\\B_WIDTH" && mkname_b_signed) {
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name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
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} else {
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mkname_last = name;
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name += stringf(":%d", p.second.as_int());
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}
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if (cell->type.in("$not", "$_NOT_"))
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mkname_a_signed = false;
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mkname_b_signed = false;
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mkname_is_signed = false;
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if (p.first == "\\A_SIGNED") {
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mkname_a_signed = true;
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mkname_is_signed = p.second.as_bool();
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}
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if (p.first == "\\B_SIGNED") {
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mkname_b_signed = true;
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mkname_is_signed = p.second.as_bool();
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}
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}
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if (cell->type.in("$not", "$_NOT_", "$pos", "$_BUF_"))
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{
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for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) {
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int A = mk.inport("\\A", i);
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int Y = mk.not_gate(A);
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int Y = cell->type.in("$not", "$_NOT_") ? mk.not_gate(A) : A;
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mk.outport(Y, "\\Y", i);
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}
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goto optimize;
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@ -256,6 +318,92 @@ Aig::Aig(Cell *cell)
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goto optimize;
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}
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if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool"))
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{
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int Y = mk.inport("\\A", 0);
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for (int i = 1; i < GetSize(cell->getPort("\\A")); i++) {
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int A = mk.inport("\\A", i);
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if (cell->type == "$reduce_and") Y = mk.and_gate(A, Y);
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if (cell->type == "$reduce_or") Y = mk.or_gate(A, Y);
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if (cell->type == "$reduce_bool") Y = mk.or_gate(A, Y);
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if (cell->type == "$reduce_xor") Y = mk.xor_gate(A, Y);
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if (cell->type == "$reduce_xnor") Y = mk.xor_gate(A, Y);
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}
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if (cell->type == "$reduce_xnor")
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Y = mk.not_gate(Y);
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mk.outport(Y, "\\Y", 0);
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for (int i = 1; i < GetSize(cell->getPort("\\Y")); i++)
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mk.outport(mk.bool_node(false), "\\Y", i);
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goto optimize;
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}
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if (cell->type.in("$logic_not", "$logic_and", "$logic_or"))
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{
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int A = mk.inport("\\A", 0), Y = -1;
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for (int i = 1; i < GetSize(cell->getPort("\\A")); i++)
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A = mk.or_gate(mk.inport("\\A", i), A);
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if (cell->type.in("$logic_and", "$logic_or")) {
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int B = mk.inport("\\B", 0);
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for (int i = 1; i < GetSize(cell->getPort("\\B")); i++)
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B = mk.or_gate(mk.inport("\\B", i), B);
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if (cell->type == "$logic_and") Y = mk.and_gate(A, B);
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if (cell->type == "$logic_or") Y = mk.or_gate(A, B);
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} else {
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if (cell->type == "$logic_not") Y = mk.not_gate(A);
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}
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mk.outport_bool(Y, "\\Y");
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goto optimize;
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}
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if (cell->type.in("$add", "$sub"))
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{
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int width = GetSize(cell->getPort("\\Y"));
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vector<int> A = mk.inport_vec("\\A", width);
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vector<int> B = mk.inport_vec("\\B", width);
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int carry = mk.bool_node(false);
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if (cell->type == "$sub") {
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for (auto &n : B)
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n = mk.not_gate(n);
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carry = mk.not_gate(carry);
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}
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vector<int> Y = mk.adder(A, B, carry);
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mk.outport_vec(Y, "\\Y");
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goto optimize;
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}
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if (cell->type == "$alu")
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{
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int width = GetSize(cell->getPort("\\Y"));
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vector<int> A = mk.inport_vec("\\A", width);
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vector<int> B = mk.inport_vec("\\B", width);
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int carry = mk.inport("\\CI");
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int binv = mk.inport("\\BI");
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for (auto &n : B)
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n = mk.xor_gate(n, binv);
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vector<int> X(width), CO(width);
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vector<int> Y = mk.adder(A, B, carry, &X, &CO);
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for (int i = 0; i < width; i++)
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X[i] = mk.xor_gate(A[i], B[i]);
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mk.outport_vec(Y, "\\Y");
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mk.outport_vec(X, "\\X");
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mk.outport_vec(CO, "\\CO");
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goto optimize;
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}
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if (cell->type.in("$eq", "$ne"))
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{
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int width = std::max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
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vector<int> A = mk.inport_vec("\\A", width);
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vector<int> B = mk.inport_vec("\\B", width);
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int Y = mk.bool_node(false);
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for (int i = 0; i < width; i++)
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Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i]));
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if (cell->type == "$eq")
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Y = mk.not_gate(Y);
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mk.outport_bool(Y, "\\Y");
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goto optimize;
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}
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if (cell->type == "$_AOI3_")
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{
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int A = mk.inport("\\A");
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