mirror of https://github.com/YosysHQ/yosys.git
Added "port_directions" to write_json output
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a1c62b79d5
commit
c0e2b3eb11
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@ -137,6 +137,19 @@ struct JsonWriter
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f << stringf(" \"attributes\": {");
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write_parameters(c->attributes);
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f << stringf("\n },\n");
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if (c->known()) {
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f << stringf(" \"port_directions\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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string direction = "output";
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if (c->input(conn.first))
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direction = c->output(conn.first) ? "inout" : "input";
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
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first2 = false;
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}
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f << stringf("\n },\n");
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}
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f << stringf(" \"connections\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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@ -240,6 +253,10 @@ struct JsonBackend : public Backend {
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log(" <attribute_name>: <attribute_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"port_directions\": {\n");
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log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"connections\": {\n");
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log(" <port_name>: <bit_vector>,\n");
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log(" ...\n");
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@ -256,6 +273,9 @@ struct JsonBackend : public Backend {
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log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
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log("automatically created and is likely not of interest for a regular user.\n");
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log("\n");
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log("The \"port_directions\" section is only included for cells for which the\n");
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log("interface is known.\n");
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log("\n");
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log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
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log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
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log("values referenced above are vectors of this integers. Signal bits that are\n");
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