mirror of https://github.com/YosysHQ/yosys.git
Added "write_aiger" command
This commit is contained in:
Clifford Wolf
parent
b1cdf772eb
commit
c1f762ca56
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@ -0,0 +1,3 @@
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OBJS += backends/aiger/aiger.o
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@ -0,0 +1,395 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void aiger_encode(std::ostream &f, int x)
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{
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log_assert(x >= 0);
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while (x & ~0x7f) {
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f.put((x & 0x7f) | 0x80);
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x = x >> 7;
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}
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f.put(x);
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}
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struct AigerWriter
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{
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Module *module;
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bool zinit_mode;
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SigMap sigmap;
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dict<SigBit, bool> init_map;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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pool<SigBit> initstate_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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dict<SigBit, int> ordered_latches;
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dict<SigBit, int> init_inputs;
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int initstate_ff = 0;
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int bit2aig(SigBit bit)
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{
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if (aig_map.count(bit) == 0)
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{
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aig_map[bit] = -1;
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if (initstate_bits.count(bit)) {
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log_assert(initstate_ff > 0);
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aig_map[bit] = initstate_ff;
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} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_m++, aig_a++;
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aig_map[bit] = 2*aig_m;
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aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
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}
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}
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log_assert(aig_map.at(bit) >= 0);
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return aig_map.at(bit);
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}
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AigerWriter(Module *module, bool zinit_mode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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{
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
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init_map[initsig[i]] = initval[i];
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}
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if (wire->port_input)
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for (auto bit : sigmap(wire))
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input_bits.insert(bit);
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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output_bits.insert(bit);
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}
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for (auto cell : module->cells())
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{
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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not_map[Y] = A;
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continue;
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}
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if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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ff_map[Q] = D;
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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and_map[Y] = make_pair(A, B);
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continue;
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}
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if (cell->type == "$initstate")
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{
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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initstate_bits.insert(Y);
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continue;
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}
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log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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init_map.sort();
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input_bits.sort();
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output_bits.sort();
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not_map.sort();
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ff_map.sort();
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and_map.sort();
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aig_map[State::S0] = 0;
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aig_map[State::S1] = 1;
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for (auto bit : input_bits) {
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aig_m++, aig_i++;
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aig_map[bit] = 2*aig_m;
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}
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if (zinit_mode)
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{
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for (auto it : ff_map) {
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if (init_map.count(it.first))
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continue;
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aig_m++, aig_i++;
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init_inputs[it.first] = 2*aig_m;
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}
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}
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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aig_map[it.first] = 2*aig_m;
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ordered_latches[it.first] = aig_l;
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if (init_map.count(it.first) == 0)
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aig_latchinit.push_back(2);
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else
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aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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}
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if (!initstate_bits.empty() || !init_inputs.empty()) {
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aig_m++, aig_l++;
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initstate_ff = 2*aig_m+1;
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aig_latchinit.push_back(0);
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}
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for (auto it : ff_map)
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aig_latchin.push_back(bit2aig(it.second));
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if (!initstate_bits.empty() || !init_inputs.empty())
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aig_latchin.push_back(1);
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for (auto bit : output_bits) {
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aig_o++;
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ordered_outputs[bit] = aig_o;
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aig_outputs.push_back(bit2aig(bit));
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode)
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{
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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log_assert(aig_l == GetSize(aig_latchinit));
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log_assert(aig_o == GetSize(aig_outputs));
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if (miter_mode)
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f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
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else
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f << stringf("%s %d %d %d %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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if (ascii_mode)
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{
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for (int i = 0; i < aig_i; i++)
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f << stringf("%d\n", 2*i+2);
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for (int i = 0; i < aig_l; i++) {
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if (aig_latchinit.at(i) == 0)
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f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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for (int i = 0; i < aig_o; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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for (int i = 0; i < aig_a; i++)
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f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
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}
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else
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{
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for (int i = 0; i < aig_l; i++) {
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if (aig_latchinit.at(i) == 0)
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f << stringf("%d\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d 1\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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for (int i = 0; i < aig_o; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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for (int i = 0; i < aig_a; i++) {
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int lhs = 2*(aig_i+aig_l+i)+2;
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int rhs0 = aig_gates.at(i).first;
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int rhs1 = aig_gates.at(i).second;
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int delta0 = lhs - rhs0;
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int delta1 = rhs0 - rhs1;
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aiger_encode(f, delta0);
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aiger_encode(f, delta1);
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}
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}
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f << stringf("c\nGenerated by %s\n", yosys_version_str);
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}
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void write_map(std::ostream &f)
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{
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dict<int, string> input_lines;
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dict<int, string> output_lines;
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dict<int, string> latch_lines;
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dict<int, string> wire_lines;
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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continue;
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(wire); i++)
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{
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if (aig_map.count(sig[i]) == 0)
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continue;
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int a = aig_map.at(sig[i]);
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// wire_lines[a] = stringf("wire %d %d %s\n", a, i, log_id(wire));
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if (wire->port_input) {
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log_assert((a & 1) == 0);
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input_lines[a] = stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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}
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if (wire->port_output) {
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int n = ordered_outputs.at(sig[i]);
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output_lines[n] = stringf("output %d %d %s\n", n-1, i, log_id(wire));
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}
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if (ordered_latches.count(sig[i])) {
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int n = ordered_latches.at(sig[i]);
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latch_lines[n] = stringf("latch %d %d %s\n", n-1, i, log_id(wire));
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}
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}
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}
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input_lines.sort();
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for (auto &it : input_lines)
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f << it.second;
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output_lines.sort();
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for (auto &it : output_lines)
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f << it.second;
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latch_lines.sort();
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for (auto &it : latch_lines)
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f << it.second;
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wire_lines.sort();
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for (auto &it : wire_lines)
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f << it.second;
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}
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};
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struct AigerBackend : public Backend {
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AigerBackend() : Backend("aiger", "write design to AIGER file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_aiger [options] [filename]\n");
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log("\n");
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log("Write the current design to an AIGER file. The design must be flattened and\n");
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log("must not contain any cell types except $_AND_, $_NOT_, and simple FF types.\n");
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log("\n");
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log(" -ascii\n");
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log(" write ASCII version of AGIER format\n");
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log("\n");
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// log(" -zinit\n");
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// log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
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// log(" uninitialized FFs.\n");
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// log("\n");
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log(" -miter\n");
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log(" design outputs are AIGER bad state properties\n");
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log("\n");
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log(" -map <filename>\n");
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log(" write an extra file with port, latch and wire mappings\n");
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log("\n");
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool ascii_mode = false;
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bool zinit_mode = false;
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bool miter_mode = false;
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std::string map_filename;
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log_header(design, "Executing AIGER backend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ascii") {
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ascii_mode = true;
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continue;
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}
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if (args[argidx] == "-zinit") {
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zinit_mode = true;
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continue;
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}
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if (args[argidx] == "-miter") {
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miter_mode = true;
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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Module *top_module = design->top_module();
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if (top_module == nullptr)
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log_error("Can't find top module in current design!\n");
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if (zinit_mode)
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log_error("zinit mode is not implemented yet.\n");
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AigerWriter writer(top_module, zinit_mode);
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writer.write_aiger(*f, ascii_mode, miter_mode);
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if (!map_filename.empty()) {
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std::ofstream mapf;
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mapf.open(map_filename.c_str(), std::ofstream::trunc);
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if (mapf.fail())
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log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
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writer.write_map(mapf);
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}
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}
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} AigerBackend;
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PRIVATE_NAMESPACE_END
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