mirror of https://github.com/YosysHQ/yosys.git
separated memory next from write cell
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bdf6b2b19a
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@ -78,7 +78,7 @@ struct BtorDumper
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std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers
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RTLIL::IdString curr_cell; //current cell being dumped
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std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
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std::set<int> mem_next; //if memory (line_number) already has next
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std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write
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BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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{
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@ -269,6 +269,45 @@ struct BtorDumper
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else return it->second;
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}
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int dump_memory_next(const RTLIL::Memory* memory)
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{
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auto mem_it = line_ref.find(memory->name);
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int address_bits = ceil(log(memory->size)/log(2));
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if(mem_it==std::end(line_ref))
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{
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log("can not write next of a memory that is not dumped yet\n");
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log_abort();
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}
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else
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{
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auto acond_list_it = mem_next.find(mem_it->second);
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if(acond_list_it!=std::end(mem_next))
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{
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std::set<std::pair<int,int>>& cond_list = acond_list_it->second;
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if(cond_list.empty())
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{
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return 0;
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}
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auto it=cond_list.begin();
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, memory->width, address_bits, it->first, it->second, mem_it->second);
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f << stringf("%s\n", str.c_str());
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++it;
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for(; it!=cond_list.end(); ++it)
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{
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, memory->width, address_bits, it->first, it->second, line_num-1);
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f << stringf("%s\n", str.c_str());
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}
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1);
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f << stringf("%s\n", str.c_str());
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return 1;
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}
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return 0;
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}
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}
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int dump_const(const RTLIL::Const* data, int width, int offset)
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{
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log("writing const \n");
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@ -775,7 +814,8 @@ struct BtorDumper
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
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//check if the memory has already next
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auto it = mem_next.find(mem);
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/*
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auto it = mem_next.find(mem);
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if(it != std::end(mem_next))
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{
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++line_num;
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@ -785,10 +825,11 @@ struct BtorDumper
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d eq 1 %d %d", line_num, mem, line_num - 1);
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str = stringf("%d eq 1 %d %d; mem invar", line_num, mem, line_num - 1);
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f << stringf("%s\n", str.c_str());
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mem = line_num - 1;
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}
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}
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*/
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++line_num;
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if(polarity)
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str = stringf("%d one 1", line_num);
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@ -804,14 +845,15 @@ struct BtorDumper
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++line_num;
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str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);
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f << stringf("%s\n", str.c_str());
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/*
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++line_num;
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str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2/*enable*/, line_num-1, mem);
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str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem);
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f << stringf("%s\n", str.c_str());
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);
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f << stringf("%s\n", str.c_str());
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mem_next.insert(mem);
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line_ref[cell->name]=line_num;
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*/
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mem_next[mem].insert(std::make_pair(line_num-1, line_num));
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}
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else if(cell->type == "$slice")
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{
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@ -975,6 +1017,12 @@ struct BtorDumper
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dump_cell(cell_it->second);
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}
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log("writing memory next");
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for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
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{
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dump_memory_next(mem_it->second);
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}
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for(auto it: safety)
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dump_property(it);
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