mirror of https://github.com/YosysHQ/yosys.git
write_xaiger to write __dummy_o__ for -symbols too
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07036b8bf7
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5180338e80
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@ -368,7 +368,7 @@ struct XAigerWriter
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool omode)
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{
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int aig_obc = aig_o;
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int aig_obcj = aig_obc;
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@ -449,6 +449,7 @@ struct XAigerWriter
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{
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dict<string, vector<string>> symbols;
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bool output_seen = false;
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for (auto wire : module->wires())
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{
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//if (wire->name[0] == '$')
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@ -458,14 +459,8 @@ struct XAigerWriter
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for (int i = 0; i < GetSize(wire); i++)
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{
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if (sig[i].wire == nullptr) {
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if (wire->port_output)
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sig[i] = SigBit(wire, i);
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else
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continue;
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}
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if (input_bits.count(sig[i]) || ci_bits.count(SigSpec(sig[i]))) {
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RTLIL::SigBit b(wire, i);
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if (input_bits.count(b) || ci_bits.count(b)) {
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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@ -474,8 +469,9 @@ struct XAigerWriter
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
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}
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if (output_bits.count(SigSpec(wire, i)) || co_bits.count(SigSpec(wire, i))) {
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int o = ordered_outputs.at(SigSpec(wire, i));
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if (output_bits.count(b) || co_bits.count(b)) {
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int o = ordered_outputs.at(b);
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output_seen = !miter_mode;
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if (GetSize(wire) != 1)
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
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else
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@ -502,6 +498,9 @@ struct XAigerWriter
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}
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}
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if (omode && !output_seen)
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symbols["o0"].push_back("__dummy_o__");
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symbols.sort();
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for (auto &sym : symbols) {
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@ -692,7 +691,7 @@ struct XAigerBackend : public Backend {
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log_error("Can't find top module in current design!\n");
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XAigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, omode);
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if (!map_filename.empty()) {
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std::ofstream mapf;
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