mirror of https://github.com/YosysHQ/yosys.git
Add state initval handling to btor back-end
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f697282246
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@ -63,6 +63,7 @@ struct BtorWorker
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pool<Cell*> cell_recursion_guard;
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pool<string> output_symbols;
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dict<SigBit, bool> initbits;
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string indent;
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void btorf(const char *fmt, ...)
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@ -101,6 +102,9 @@ struct BtorWorker
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void add_nid_sig(int nid, const SigSpec &sig)
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{
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if (verbose)
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f << indent << stringf("; %d %s\n", nid, log_signal(sig));
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for (int i = 0; i < GetSize(sig); i++)
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bit_nid[sig[i]] = make_pair(nid, i);
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@ -492,6 +496,20 @@ struct BtorWorker
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else
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btorf("%d state %d %s\n", nid, sid, symbol.c_str());
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Const initval;
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for (int i = 0; i < GetSize(sig_q); i++)
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if (initbits.count(sig_q[i]))
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initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
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else
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initval.bits.push_back(State::Sx);
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if (!initval.is_fully_undef()) {
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int nid_init_val = get_sig_nid(initval);
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int nid_init = next_nid++;
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btorf("; initval = %s\n", log_signal(initval));
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btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
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}
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ff_todo.push_back(make_pair(nid, cell));
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add_nid_sig(nid, sig_q);
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goto okay;
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@ -694,6 +712,13 @@ struct BtorWorker
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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Const attrval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
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if (attrval[i] == State::S0 || attrval[i] == State::S1)
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initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
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}
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if (!wire->port_id || !wire->port_input)
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continue;
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