riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Minor improvements to smtio.py vcd writer

This commit is contained in:
Clifford Wolf 2016-09-10 16:24:08 +02:00
parent b582f11074
commit 5199aafca0
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
backends/smt2/smtio.py
View File

@ -593,6 +593,7 @@ class MkVcd:
assert t >= self.t
if t != self.t:
if self.t == -1:
print("$var integer 32 t smt_step $end", file=self.f)
print("$var event 1 ! smt_clock $end", file=self.f)
scope = []
for path in sorted(self.nets):
@ -609,6 +610,7 @@ class MkVcd:
print("$enddefinitions $end", file=self.f)
self.t = t
assert self.t >= 0
print("#%d" % self.t, file=self.f)
print("#%d" % (10 * self.t), file=self.f)
print("1!", file=self.f)
print("b%s t" % format(self.t, "032b"), file=self.f)