mirror of https://github.com/YosysHQ/yosys.git
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
This commit is contained in:
luke whittlesey
parent
08f9b38a9c
commit
a8fe040906
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@ -38,7 +38,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool norename, noattr, attr2comment, noexpr;
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bool norename, noattr, attr2comment, noexpr, nomem;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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@ -791,14 +791,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == "$mem" && false) // FIXME!
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if (cell->type == "$mem" && nomem == false)
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{
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RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
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std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
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int abits = cell->parameters["\\ABITS"].as_int();
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int size = cell->parameters["\\SIZE"].as_int();
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int width = cell->parameters["\\WIDTH"].as_int();
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int offset = cell->parameters["\\OFFSET"].as_int();
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bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef());
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// for memory block make something like:
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@ -807,12 +806,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// memid[0] <= ...
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// end
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int mem_val;
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RTLIL::Memory memory;
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memory.name = memid;
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memory.width = width;
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memory.start_offset = offset;
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memory.size = size;
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dump_memory(f, indent.c_str(), &memory);
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f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0);
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if (use_init)
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{
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f << stringf("%s" "initial begin\n", indent.c_str());
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@ -844,7 +838,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// temp_id <= array_reg[r_addr];
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// assign r_data = temp_id;
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std::string temp_id = next_auto_id();
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f << stringf("%s" "reg [%d:0] %s;\n", indent.c_str(), sig_rd_addr.size() - 1, temp_id.c_str());
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f << stringf("%s" "reg [%d:0] %s;\n", indent.c_str(), sig_rd_data.size() - 1, temp_id.c_str());
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f << stringf("%s" "always @(%sedge ", indent.c_str(), rd_clk_posedge ? "pos" : "neg");
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dump_sigspec(f, sig_rd_clk);
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f << stringf(")\n");
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@ -886,7 +880,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int();
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RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en, sig_wr_en_bit;
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RTLIL::SigBit last_bit, current_bit;
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RTLIL::SigBit last_bit;
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bool wr_clk_posedge;
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RTLIL::SigSpec lof_wen;
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dict<RTLIL::SigSpec, int> wen_to_width;
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@ -910,9 +904,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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lof_wen = RTLIL::SigSpec(last_bit);
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wen_to_width.clear();
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wen_to_width[last_bit] = 0;
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for (int j=0; j<width; j++)
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for (auto ¤t_bit : sig_wr_en.bits())
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{
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current_bit = sig_wr_en.extract(j);
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if (sigmap(current_bit) == sigmap(last_bit)){
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wen_to_width[current_bit] += 1;
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} else {
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@ -924,7 +917,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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// make something like:
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// always @(posedge clk)
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// if (wr_en_bit)
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// memid[w_addr][??] <= w_data[??];
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// memid[w_addr][??] <= w_data[??];
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// ...
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n = 0;
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for (auto &wen_bit : lof_wen) {
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@ -1292,6 +1285,10 @@ struct VerilogBackend : public Backend {
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log(" only write selected modules. modules must be selected entirely or\n");
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log(" not at all.\n");
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log("\n");
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log(" -nomem\n");
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log(" do not create verilog code for $mem cells. This is only used for\n");
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log(" testing.\n");
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log("\n");
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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@ -1301,6 +1298,7 @@ struct VerilogBackend : public Backend {
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noattr = false;
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attr2comment = false;
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noexpr = false;
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nomem = false;
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bool blackboxes = false;
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bool selected = false;
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@ -1358,6 +1356,10 @@ struct VerilogBackend : public Backend {
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selected = true;
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continue;
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}
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if (arg == "-nomem") {
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nomem = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -1,7 +1,9 @@
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#!/bin/bash
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set -e
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../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
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-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
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../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full; write_verilog temp/synth_${1}_${2}_stage0.v" \
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-l temp/synth_${1}_${2}_stage0.log temp/brams_${1}.v
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../../yosys -qq -p "proc; opt; memory -nomap; opt -fast -full; write_verilog -nomem temp/synth_${1}_${2}.v" \
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-l temp/synth_${1}_${2}.log temp/synth_${1}_${2}_stage0.v
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iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
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temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
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temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
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