mirror of https://github.com/YosysHQ/yosys.git
Progress in SMV back-end
This commit is contained in:
Clifford Wolf
parent
8c79765de5
commit
6c6bf4999e
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@ -40,13 +40,8 @@ struct SmvWorker
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pool<shared_str> used_names;
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vector<shared_str> strbuf;
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struct assign_rhs_chunk {
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string rhs_expr;
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int offset, width;
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bool operator<(const assign_rhs_chunk &other) const { return offset < other.offset; }
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};
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dict<Wire*, vector<assign_rhs_chunk>> partial_assignments;
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pool<Wire*> partial_assignment_wires;
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dict<SigBit, std::pair<const char*, int>> partial_assignment_bits;
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vector<string> assignments;
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const char *cid()
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@ -109,13 +104,44 @@ struct SmvWorker
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}
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}
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const char *rvalue(SigSpec sig, bool skip_sigmap = false, int width = -1, bool is_signed = false)
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const char *rvalue(SigSpec sig, int width = -1, bool is_signed = false)
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{
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if (!skip_sigmap)
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sigmap.apply(sig);
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string s;
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int count_chunks = 0;
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sigmap.apply(sig);
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for (int i = 0; i < GetSize(sig); i++)
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if (partial_assignment_bits.count(sig[i]))
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{
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int width = 1;
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const auto &bit_a = partial_assignment_bits.at(sig[i]);
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while (i+width < GetSize(sig))
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{
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if (!partial_assignment_bits.count(sig[i+width]))
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break;
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const auto &bit_b = partial_assignment_bits.at(sig[i+width]);
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if (strcmp(bit_a.first, bit_b.first))
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break;
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if (bit_a.second+width != bit_b.second)
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break;
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width++;
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}
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if (i+width < GetSize(sig))
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s = stringf("%s :: ", rvalue(sig.extract(i+width, GetSize(sig)-(width+i))));
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s += stringf("%s[%d:%d]", bit_a.first, bit_a.second+width-1, bit_a.second);
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if (i > 0)
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s += stringf(" :: %s", rvalue(sig.extract(0, i)));
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count_chunks = 3;
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goto continue_with_resize;
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}
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for (auto &c : sig.chunks()) {
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count_chunks++;
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if (!s.empty())
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@ -133,6 +159,7 @@ struct SmvWorker
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}
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}
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continue_with_resize:;
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if (width >= 0) {
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if (is_signed) {
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if (GetSize(sig) > width)
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@ -152,40 +179,29 @@ struct SmvWorker
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const char *rvalue_u(SigSpec sig, int width = -1)
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{
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return rvalue(sig, false, width, false);
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return rvalue(sig, width, false);
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}
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const char *rvalue_s(SigSpec sig, int width = -1, bool is_signed = true)
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{
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return rvalue(sig, false, width, is_signed);
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return rvalue(sig, width, is_signed);
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}
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const char *lvalue(SigSpec sig, bool skip_sigmap = false)
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const char *lvalue(SigSpec sig)
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{
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if (!skip_sigmap)
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sigmap.apply(sig);
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sigmap.apply(sig);
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if (sig.is_wire())
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return rvalue(sig, true);
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return rvalue(sig);
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const char *temp_id = cid();
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f << stringf(" %s : unsigned word[%d]; -- %s\n", temp_id, GetSize(sig), log_signal(sig));
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int offset = 0;
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for (auto &c : sig.chunks())
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{
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log_assert(c.wire != nullptr);
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assign_rhs_chunk rhs;
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if (offset != 0 || c.width != GetSize(sig))
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rhs.rhs_expr = stringf("%s[%d:%d]", temp_id, offset+c.width-1, offset);
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else
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rhs.rhs_expr = temp_id;
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rhs.offset = c.offset;
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rhs.width = c.width;
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partial_assignments[c.wire].push_back(rhs);
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offset += c.width;
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for (auto bit : sig) {
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log_assert(bit.wire != nullptr);
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partial_assignment_wires.insert(bit.wire);
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partial_assignment_bits[bit] = std::pair<const char*, int>(temp_id, offset++);
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}
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return temp_id;
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@ -198,28 +214,10 @@ struct SmvWorker
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for (auto wire : module->wires())
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{
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SigSpec this_sig = wire, driver_sig = sigmap(wire);
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SigSpec unused_bits_in_this_sig;
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SigSpec driver_for_unused_bits;
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if (SigSpec(wire) != sigmap(wire))
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partial_assignment_wires.insert(wire);
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for (int i = 0; i < GetSize(this_sig); i++)
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if (this_sig[i] != driver_sig[i]) {
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unused_bits_in_this_sig.append(this_sig[i]);
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driver_for_unused_bits.append(driver_sig[i]);
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}
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if (GetSize(unused_bits_in_this_sig) == GetSize(this_sig))
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{
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f << stringf(" -- unused -- %s : unsigned word[%d]; -- %s\n", cid(wire->name), wire->width, log_id(wire));
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}
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else
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{
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f << stringf(" %s : unsigned word[%d]; -- %s\n", cid(wire->name), wire->width, log_id(wire));
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if (!unused_bits_in_this_sig.empty())
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assignments.push_back(stringf("%s := 0ub%d_0; -- unused %s -- using %s instead", lvalue(unused_bits_in_this_sig, true),
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GetSize(unused_bits_in_this_sig), log_signal(unused_bits_in_this_sig), log_signal(driver_for_unused_bits)));
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}
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f << stringf(" %s : unsigned word[%d]; -- %s\n", cid(wire->name), wire->width, log_id(wire));
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}
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for (auto cell : module->cells())
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@ -562,23 +560,76 @@ struct SmvWorker
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assignments.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
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}
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for (auto &it : partial_assignments)
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for (Wire *wire : partial_assignment_wires)
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{
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std::sort(it.second.begin(), it.second.end());
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string expr;
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int offset = 0;
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for (auto rhs : it.second) {
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for (int i = 0; i < wire->width; i++)
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{
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SigBit bit = sigmap(SigBit(wire, i));
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if (!expr.empty())
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expr = " :: " + expr;
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if (offset < rhs.offset)
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expr = stringf(" :: 0ub%d_0 ", rhs.offset - offset) + expr;
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expr = rhs.rhs_expr + expr;
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offset = rhs.offset + rhs.width;
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if (partial_assignment_bits.count(bit))
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{
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int width = 1;
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const auto &bit_a = partial_assignment_bits.at(bit);
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while (i+1 < wire->width)
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{
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SigBit next_bit = sigmap(SigBit(wire, i+1));
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if (!partial_assignment_bits.count(next_bit))
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break;
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const auto &bit_b = partial_assignment_bits.at(next_bit);
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if (strcmp(bit_a.first, bit_b.first))
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break;
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if (bit_a.second+width != bit_b.second)
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break;
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width++, i++;
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}
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expr = stringf("%s[%d:%d]", bit_a.first, bit_a.second+width-1, bit_a.second) + expr;
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}
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else if (sigmap(SigBit(wire, i)).wire == nullptr)
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{
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string bits;
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SigSpec sig = sigmap(SigSpec(wire, i));
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while (i+1 < wire->width) {
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SigBit next_bit = sigmap(SigBit(wire, i+1));
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if (next_bit.wire != nullptr)
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break;
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sig.append(next_bit);
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i++;
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}
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for (int k = GetSize(sig)-1; k >= 0; k--)
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bits += sig[k] == State::S1 ? '1' : '0';
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expr = stringf("0ub%d_%s", GetSize(bits), bits.c_str()) + expr;
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}
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else
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{
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string bits;
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SigSpec sig = sigmap(SigSpec(wire, i));
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while (i+1 < wire->width) {
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SigBit next_bit = sigmap(SigBit(wire, i+1));
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if (next_bit.wire == nullptr || partial_assignment_bits.count(next_bit))
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break;
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sig.append(next_bit);
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i++;
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}
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expr = rvalue(sig) + expr;
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}
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}
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if (offset < it.first->width)
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expr = stringf("0ub%d_0 :: ", it.first->width - offset) + expr;
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assignments.push_back(stringf("%s := %s;", cid(it.first->name), expr.c_str()));
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assignments.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str()));
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}
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f << stringf(" ASSIGN\n");
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