mirror of https://github.com/YosysHQ/yosys.git
More progress on Firrtl backend.
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
This commit is contained in:
Adam Izraelevitz
parent
69468d5a16
commit
794cec0016
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@ -157,7 +157,53 @@ struct FirrtlWorker
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for (auto cell : module->cells())
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{
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if (cell->type.in("$add", "$sub", "$xor"))
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if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
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{
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string y_id = make_id(cell->name);
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bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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int y_width = cell->parameters.at("\\Y_WIDTH").as_int();
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string a_expr = make_expr(cell->getPort("\\A"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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if (cell->parameters.at("\\A_SIGNED").as_bool()) {
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a_expr = "asSInt(" + a_expr + ")";
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}
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a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
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string primop;
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bool always_uint = false;
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if (cell->type == "$not") primop = "not";
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if (cell->type == "$neg") primop = "neg";
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if (cell->type == "$logic_not") {
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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if (cell->type == "$reduce_and") primop = "andr";
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if (cell->type == "$reduce_or") primop = "orr";
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if (cell->type == "$reduce_xor") primop = "xorr";
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if (cell->type == "$reduce_xnor") {
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr.c_str());
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}
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if (cell->type == "$reduce_bool") {
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primop = "neq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str());
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if ((is_signed && !always_uint))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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}
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$and", "$or", "$eq", "$eqx",
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or"))
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{
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string y_id = make_id(cell->name);
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bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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@ -166,22 +212,88 @@ struct FirrtlWorker
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string b_expr = make_expr(cell->getPort("\\B"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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if (is_signed) {
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if (cell->parameters.at("\\A_SIGNED").as_bool()) {
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a_expr = "asSInt(" + a_expr + ")";
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}
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if (cell->parameters.at("\\A_SIGNED").as_bool() & (cell->type != "$shr")) {
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b_expr = "asSInt(" + b_expr + ")";
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}
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a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
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b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
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if ((cell->type != "$shl") && (cell->type != "$sshl")) {
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b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
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}
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if (cell->parameters.at("\\A_SIGNED").as_bool() & (cell->type == "$shr")) {
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a_expr = "asUInt(" + a_expr + ")";
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}
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string primop;
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bool always_uint = false;
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if (cell->type == "$add") primop = "add";
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if (cell->type == "$sub") primop = "sub";
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if (cell->type == "$xor") primop = "xor";
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if (cell->type == "$mul") primop = "mul";
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if (cell->type == "$div") primop = "div";
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if (cell->type == "$mod") primop = "rem";
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if (cell->type == "$and") {
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primop = "and";
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always_uint = true;
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}
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if (cell->type == "$or" ) {
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primop = "or";
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always_uint = true;
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}
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if (cell->type == "$xor") {
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primop = "xor";
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always_uint = true;
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}
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if ((cell->type == "$eq") | (cell->type == "$eqx")) {
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primop = "eq";
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always_uint = true;
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}
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if ((cell->type == "$ne") | (cell->type == "$nex")) {
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primop = "neq";
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always_uint = true;
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}
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if (cell->type == "$gt") {
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primop = "gt";
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always_uint = true;
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}
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if (cell->type == "$ge") {
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primop = "geq";
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always_uint = true;
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}
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if (cell->type == "$lt") {
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primop = "lt";
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always_uint = true;
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}
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if (cell->type == "$le") {
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primop = "leq";
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always_uint = true;
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}
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if ((cell->type == "$shl") | (cell->type == "$sshl")) primop = "dshl";
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if ((cell->type == "$shr") | (cell->type == "$sshr")) primop = "dshr";
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if ((cell->type == "$logic_and")) {
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primop = "and";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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}
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if ((cell->type == "$logic_or")) {
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primop = "or";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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}
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if (!cell->parameters.at("\\B_SIGNED").as_bool()) {
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b_expr = "asUInt(" + b_expr + ")";
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}
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string expr = stringf("%s(%s, %s)", primop.c_str(), a_expr.c_str(), b_expr.c_str());
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if ((is_signed && !cell->type.in("$xor")) || cell->type.in("$sub"))
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if ((is_signed && !always_uint) || cell->type.in("$sub"))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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@ -1,16 +1,20 @@
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#!/bin/bash
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set -ex
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../../yosys -p 'prep -nordff; write_firrtl test.fir' test.v
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cd ../../
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make
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cd backends/firrtl
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firrtl -i test.fir -o test_out.v
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../../yosys -q -p 'prep -nordff; write_firrtl test.fir' $1
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../../yosys -p '
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read_verilog test.v
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rename test gold
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firrtl -i test.fir -o test_out.v -ll Info
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../../yosys -p "
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read_verilog $1
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rename Top gold
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read_verilog test_out.v
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rename test gate
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rename Top gate
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prep
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memory_map
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@ -18,5 +22,4 @@ firrtl -i test.fir -o test_out.v
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hierarchy -top miter
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sat -verify -prove trigger 0 -set-init-zero -seq 10 miter
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'
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"
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@ -1,24 +1,63 @@
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module test(
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input clk, wen,
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input [4:0] waddr, raddr,
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input [31:0] wdata,
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output reg [31:0] rdata,
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signed input [7:0] a, b, x,
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output [15:0] s, d, y, z, u, q
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input [7:0] uns,
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input signed [7:0] a, b,
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input signed [23:0] c,
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input signed [2:0] sel,
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output [15:0] s, d, y, z, u, q, p, mul, div, mod, mux, And, Or, Xor, eq, neq, gt, lt, geq, leq, eqx, shr, sshr, shl, sshl, Land, Lor, Lnot, Not, Neg, pos, Andr, Orr, Xorr, Xnorr, Reduce_bool,
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output [7:0] PMux
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);
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reg [31:0] memory [0:31];
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always @(posedge clk) begin
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rdata <= memory[raddr];
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if (wen) memory[waddr] <= wdata;
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end
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//initial begin
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//$display("shr = %b", shr);
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//end
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assign s = a+{b[6:2], 2'b1};
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assign d = a-b;
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assign y = x;
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assign z[7:0] = s+d;
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assign z[15:8] = s-d;
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assign p = a & b | x;
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assign mul = a * b;
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assign div = a / b;
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assign mod = a % b;
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assign mux = x[0] ? a : b;
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assign And = a & b;
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assign Or = a | b;
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assign Xor = a ^ b;
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assign Not = ~a;
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assign Neg = -a;
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assign eq = a == b;
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assign neq = a != b;
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assign gt = a > b;
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assign lt = a < b;
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assign geq = a >= b;
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assign leq = a <= b;
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assign eqx = a === b;
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assign shr = a >> b; //0111111111000000
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assign sshr = a >>> b;
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assign shl = a << b;
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assign sshl = a <<< b;
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assign Land = a && b;
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assign Lor = a || b;
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assign Lnot = !a;
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assign pos = $signed(uns);
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assign Andr = &a;
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assign Orr = |a;
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assign Xorr = ^a;
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assign Xnorr = ~^a;
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always @*
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if(!a) begin
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Reduce_bool = a;
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end else begin
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Reduce_bool = b;
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end
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//always @(sel or c or a)
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// begin
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// case (sel)
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// 3'b000: PMux = a;
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// 3'b001: PMux = c[7:0];
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// 3'b010: PMux = c[15:8];
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// 3'b100: PMux = c[23:16];
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// endcase
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// end
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always @(posedge clk)
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q <= s ^ d ^ x;
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endmodule
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