mirror of https://github.com/YosysHQ/yosys.git
Use log_abort() and log_assert() in BTOR backend
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parent
54d74cf616
commit
f7bd0a5232
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@ -28,7 +28,6 @@
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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#include <assert.h>
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#include <math.h>
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struct BtorDumperConfig
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@ -244,7 +243,7 @@ struct BtorDumper
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return it->second;
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}
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}
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assert(false);
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log_abort();
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return -1;
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}
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@ -283,7 +282,7 @@ struct BtorDumper
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}
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else
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log("writing const error\n");
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assert(false);
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log_abort();
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return -1;
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}
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@ -302,7 +301,7 @@ struct BtorDumper
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else
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{
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int wire_line_num = dump_wire(chunk->wire);
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assert(wire_line_num>0);
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log_assert(wire_line_num>0);
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++line_num;
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str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num,
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chunk->width + chunk->offset - 1, chunk->offset);
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@ -329,12 +328,12 @@ struct BtorDumper
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{
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int l1, l2, w1, w2;
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l1 = dump_sigchunk(&s.chunks[0]);
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assert(l1>0);
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log_assert(l1>0);
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w1 = s.chunks[0].width;
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for (unsigned i=1; i < s.chunks.size(); ++i)
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{
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l2 = dump_sigchunk(&s.chunks[i]);
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assert(l2>0);
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log_assert(l2>0);
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w2 = s.chunks[i].width;
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++line_num;
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str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
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@ -374,7 +373,7 @@ struct BtorDumper
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l = line_num;
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}
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}
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assert(l>0);
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log_assert(l>0);
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return l;
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}
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@ -390,8 +389,8 @@ struct BtorDumper
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log("writing assert cell - %s\n", cstr(cell->type));
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const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
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const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
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assert(expr->width == 1);
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assert(en->width == 1);
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log_assert(expr->width == 1);
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log_assert(en->width == 1);
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int expr_line = dump_sigspec(expr, 1);
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int en_line = dump_sigspec(en, 1);
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int one_line = ++line_num;
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@ -444,7 +443,7 @@ struct BtorDumper
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log("writing unary cell - %s\n", cstr(cell->type));
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int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
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assert(output_width == 1);
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log_assert(output_width == 1);
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int l = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), w);
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if(cell->type == "$logic_not" && w > 1)
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{
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@ -470,7 +469,7 @@ struct BtorDumper
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{
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log("writing binary cell - %s\n", cstr(cell->type));
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int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
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assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
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log_assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
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cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
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bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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@ -511,7 +510,7 @@ struct BtorDumper
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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assert(l1_signed == l2_signed);
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log_assert(l1_signed == l2_signed);
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l1_width = l1_width > output_width ? l1_width : output_width;
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l1_width = l1_width > l2_width ? l1_width : l2_width;
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l2_width = l2_width > l1_width ? l2_width : l1_width;
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@ -592,7 +591,7 @@ struct BtorDumper
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{
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log("writing binary cell - %s\n", cstr(cell->type));
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int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
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assert(output_width == 1);
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log_assert(output_width == 1);
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int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), output_width);
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int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), output_width);
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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@ -653,7 +652,7 @@ struct BtorDumper
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for(unsigned i=0; i<cell_output->chunks.size(); ++i)
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{
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output_width = cell_output->chunks[i].width;
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assert( output_width == cell_output->chunks[i].wire->width);//full reg is given the next value
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log_assert( output_width == cell_output->chunks[i].wire->width);//full reg is given the next value
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int reg = dump_wire(cell_output->chunks[i].wire);//register
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int slice = value;
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if(cell_output->chunks.size()>1)
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@ -760,11 +759,11 @@ struct BtorDumper
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log("writing slice cell\n");
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const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
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int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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assert(input->width == input_width);
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log_assert(input->width == input_width);
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int input_line = dump_sigspec(input, input_width);
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const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
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int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
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assert(output->width == output_width);
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log_assert(output->width == output_width);
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int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
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++line_num;
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str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);
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@ -776,11 +775,11 @@ struct BtorDumper
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log("writing concat cell\n");
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const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
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int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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assert(input_a->width == input_a_width);
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log_assert(input_a->width == input_a_width);
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int input_a_line = dump_sigspec(input_a, input_a_width);
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const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
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int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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assert(input_b->width == input_b_width);
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log_assert(input_b->width == input_b_width);
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int input_b_line = dump_sigspec(input_b, input_b_width);
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++line_num;
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str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width,
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