Marcelina Kościelnicka
4746ffd7b2
assertpmux: Fix crash on unused $pmux output.
...
Fixes #2595 .
2021-02-22 23:30:28 +01:00
whitequark
01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse
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verilog: support recursive functions using ternary expressions
2021-02-21 20:56:04 +00:00
Zachary Snow
b6af90fe20
verilog: fix sizing of constant args for tasks/functions
...
- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
2021-02-21 15:44:43 -05:00
Zachary Snow
220cb1f7bb
verilog: error on macro invocations with missing argument lists
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This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
Zachary Snow
8de2e863af
verilog: support recursive functions using ternary expressions
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This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
whitequark
326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
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verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
Zachary Snow
73d611990d
Merge pull request #2578 from zachjs/genblk-port
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verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
Kamil Rakoczy
7533534429
Add missing is_signed to type_atom
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-11 15:05:38 +01:00
Zachary Snow
1d5f3fe506
verlog: allow shadowing module ports within generate blocks
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This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
Zachary Snow
4b2f977331
genrtlil: fix signed port connection codegen failures
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This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
Kamil Rakoczy
98c4feb72f
Add check of begin/end labels for genblock
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00
Zachary Snow
b93b6f4285
verilog: refactored constant function evaluation
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Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
whitequark
baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
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verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
whitequark
4bc6995b9a
Merge pull request #2436 from dalance/fix_generate
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Fix begin/end in generate
2021-02-03 09:43:23 +00:00
Zachary Snow
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Zachary Snow
27257a419f
verilog: strip leading and trailing spaces in macro args
2021-01-28 11:26:35 -05:00
Marcelina Kościelnicka
ea79e16bab
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
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The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll. Just assume false if the
parameter doesn't exist.
Fixes #2559 .
2021-01-27 00:32:00 +01:00
whitequark
ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
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verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
Zachary Snow
1096b969ef
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
Zachary Snow
006c18fc11
sv: fix support wire and var data type modifiers
2021-01-20 09:16:21 -07:00
Zachary Snow
4fadcc8f25
verilog: allow spaces in macro arguments
2021-01-20 08:49:58 -07:00
whitequark
e991ceeef3
Merge pull request #2547 from zachjs/plugin-so-dsym
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Add plugin.so.dSYM to .gitignore
2021-01-18 20:21:20 +00:00
Zachary Snow
4c108b4419
Add plugin.so.dSYM to .gitignore
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This artifact is automatically generated by the builtin clang on macOS
when -g is used.
2021-01-18 11:13:21 -07:00
Kamil Rakoczy
d69ddf19da
Add typedef input/output test
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
Marcelina Kościelnicka
01626e6746
opt_share: Fix X and CO signal width for shifted $alu in opt_share.
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These need to be the same length as actual Y, not visible part of Y.
Fixes #2538 .
2021-01-14 14:54:08 +01:00
whitequark
bc2de4567c
Merge pull request #2518 from zachjs/recursion
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verilog: improved support for recursive functions
2021-01-01 09:32:26 +00:00
Zachary Snow
2085d9a55d
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
Zachary Snow
75abd90829
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
Zachary Snow
750831e3e0
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
Zachary Snow
1419c8761c
Fix constants bound to redeclared function args
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The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
2020-12-26 08:48:01 -07:00
whitequark
deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
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genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
whitequark
8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width
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Fix constants bound to single bit arguments (fixes #2383 )
2020-12-23 23:15:30 +00:00
Zachary Snow
999eec5617
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
Zachary Snow
8206546c45
Fix constants bound to single bit arguments ( fixes #2383 )
2020-12-22 17:01:03 -07:00
whitequark
3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint
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Allow constant function calls in constant function arguments
2020-12-22 01:31:25 +00:00
Zachary Snow
0d8e5d965f
Sign extend port connections where necessary
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- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
Zachary Snow
186d6df4c3
Allow constant function calls in constant function arguments
2020-12-07 13:53:27 -07:00
Claire Xen
cf67e6a397
Merge pull request #2133 from dh73/nodev_head
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Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-11-25 09:44:23 +01:00
David Shah
9f241c9a42
nexus: DSP inference support
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Signed-off-by: David Shah <dave@ds0.me>
2020-11-20 08:45:55 +00:00
dalance
84ecb321b4
Fix begin/end in generate
2020-11-11 12:03:37 +09:00
Xiretza
86e0440da9
Update nexus arch tests to new harness
2020-10-29 14:42:07 +01:00
Marcelina Kościelnicka
d3b6b7fe98
xilinx: Fix attributes_test.ys
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This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.
The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
2020-10-24 23:52:37 +02:00
Marcelina Kościelnicka
eb76d35e80
memory_dff: Fix needlessly duplicating enable bits.
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When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow. Fix this by adding a simple cache.
Fixes #2409 .
2020-10-22 13:03:42 +02:00
Miodrag Milanović
ac0bd2ffc4
Merge pull request #2397 from daveshah1/nexus
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synth_nexus: Initial implementation
2020-10-19 11:20:56 +02:00
David Shah
4d584d9319
synth_nexus: Initial implementation
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 08:52:15 +01:00
Marcelina Kościelnicka
7670a89e1f
opt_clean: Better memory handling.
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Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
2020-10-08 18:05:51 +02:00
clairexen
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
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Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
clairexen
2412e75495
Merge pull request #2380 from Xiretza/parallel-tests
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Clean up and parallelize testsuite
2020-10-01 18:12:31 +02:00
David Shah
c4bfbecca6
Update .gitignore
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 15:53:14 +01:00
N. Engelhardt
dc4a617694
add tests
2020-09-28 18:16:08 +02:00
Xiretza
bed14241ef
tests: add gitignores for auto-generated makefiles
2020-09-26 16:28:24 +02:00
Eddie Hung
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default ( #2325 )
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* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00
N. Engelhardt
370243426e
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
Xiretza
e38b830cbb
tests/simple: remove "nullglob" shopt
2020-09-21 15:07:02 +02:00
Xiretza
01260344d3
tests: Parallelize
2020-09-21 15:07:02 +02:00
Xiretza
acd47bbd52
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
clairexen
f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size
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Rewrite multirange arrays sizes [n] as [n-1:0]
2020-09-17 18:27:05 +02:00
clairexen
9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
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Fix unsupported subarray access detection
2020-09-17 18:21:53 +02:00
Udi Finkelstein
7ed0e23e19
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-17 00:55:17 +03:00
Udi Finkelstein
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
Miodrag Milanović
da3002e580
Merge pull request #2369 from Xiretza/gitignores
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Add missing gitignores for test artifacts
2020-09-10 13:37:49 +02:00
clairexen
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam
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Allow localparams in constant functions
2020-09-01 17:31:48 +02:00
clairexen
3e1840d036
Merge pull request #2353 from zachjs/top-scope
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Module name scope support
2020-09-01 17:30:09 +02:00
clairexen
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type
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Fix constant args used with function ports split across declarations
2020-09-01 17:28:35 +02:00
Xiretza
6224fd9055
Add missing gitignores for test artifacts
2020-08-31 19:43:51 +02:00
Zachary Snow
ecc5c23b4d
Fix constant args used with function ports split across declarations
2020-08-29 13:31:02 -04:00
whitequark
2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
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flatten, techmap: don't canonicalize tpl driven bits via sigmap
2020-08-27 11:28:31 +00:00
Dan Ravensloft
1a07b330f8
intel_alm: Add multiply signedness to cells
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Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
whitequark
9f0892159e
flatten, techmap: don't canonicalize tpl driven bits via sigmap.
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For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in 9f772eb9
.
Fixes #2183 .
2020-08-26 16:29:42 +00:00
Zachary Snow
6127f22788
Module name scope support
2020-08-20 20:15:08 -04:00
Zachary Snow
74abc3bbfd
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
clairexen
d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
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techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 16:25:56 +02:00
clairexen
a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes
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opt_share: Refactor, fix some bugs.
2020-08-20 16:24:53 +02:00
clairexen
799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed
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peeopt.shiftmul: Add a signedness check.
2020-08-20 16:23:07 +02:00
clairexen
6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
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Remove passes redundant with opt_dff
2020-08-20 16:21:58 +02:00
clairexen
faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix
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techmap.CONSTMAP: Handle outputs before inputs.
2020-08-20 16:21:09 +02:00
clairexen
16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign
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peepopt.muldiv: Add a signedness check.
2020-08-20 16:19:37 +02:00
Marcelina Kościelnicka
50d532f01c
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
...
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering. This path was needlessly
overcomplicated and contained bugs.
Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling). This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.
Fixes #2346 .
2020-08-20 12:44:09 +02:00
clairexen
87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2
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Support 2D bit arrays in structures. Optimise array indexing.
2020-08-19 17:58:37 +02:00
N. Engelhardt
850f66cfdd
include both power-of-two and non-power-of-two testcases
2020-08-18 18:54:22 +02:00
clairexen
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
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Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
clairexen
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
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Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
clairexen
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
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Fix generate scoping issues
2020-08-18 17:37:11 +02:00
Claire Wolf
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
clairexen
5ee9349647
Merge pull request #2281 from zachjs/const-real
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Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
Marcelina Kościelnicka
2b777bbda8
opt_share: Refactor, fix some bugs.
...
Fixes #2334 .
Fixes #2335 .
Fixes #2336 .
2020-08-17 17:26:36 +02:00
Zachary Snow
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
Zachary Snow
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
Marcelina Kościelnicka
5693386a4e
Remove now-redundant dff2dffs pass.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
a0e99a9f3f
peepopt: Remove now-redundant dffmux pattern.
2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
c1ed1c28be
peeopt.shiftmul: Add a signedness check.
...
Fixes #2332 .
2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka
b4a4cb081d
techmap.CONSTMAP: Handle outputs before inputs.
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Fixes #2321 .
2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka
e89cc9c02f
peepopt.muldiv: Add a signedness check.
...
Fixes #2318 .
2020-08-04 16:30:24 +02:00
Lukasz Dalek
daee2d967f
Add test for subarray access on multidimensional arrays
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 17:07:33 +02:00
Lukasz Dalek
6e78f3a197
Test multirange (unpacked) arrays size
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 15:34:55 +02:00
Zachary Snow
c3e95eb1ab
Fix generate scoping issues
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- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
Marcelina Kościelnicka
18ad56ef41
Add dffunmap pass.
...
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka
6cd135a5eb
opt_expr: Remove -clkinv option, make it the default.
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Adds -noclkinv option just in case the old behavior was actually useful
to someone.
2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka
cf60699884
synth_ice40: Use opt_dff.
...
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
8501342fc5
synth_xilinx: Use opt_dff.
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The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:09 +02:00
Marcelina Kościelnicka
af6623ebb8
Add opt_dff pass.
2020-07-30 18:27:04 +02:00
Marcelina Kościelnicka
dc18bf1969
opt_expr: Fix handling of $_XNOR_ cells with A = B.
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Fixes #2311 .
2020-07-29 12:41:43 +02:00
clairexen
66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
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equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-28 12:56:22 +02:00
Marcelina Kościelnicka
a1a0abf52a
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
...
Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
2020-07-27 18:36:13 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
...
This reverts commit a3a90f6377
.
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
clairexen
9bcde4d82b
Merge pull request #2299 from zachjs/arg-loop
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Avoid generating wires for function args which are constant
2020-07-26 21:34:55 +02:00
Zachary Snow
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
Zachary Snow
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
Marcelina Kościelnicka
1c8483b7dd
zinit: Refactor to use FfInitVals.
2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka
abe4e9e607
clk2fflogic: Support all FF types.
2020-07-24 03:19:48 +02:00
Marcelina Kościelnicka
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
clairexen
c0ad522cf6
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname
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techmap: Add _TECHMAP_CELLNAME_ special parameter.
2020-07-23 18:39:42 +02:00
Dan Ravensloft
4d9d90079c
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
Marcelina Kościelnicka
dc07ae9677
techmap: Add _TECHMAP_CELLNAME_ special parameter.
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This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Zachary Snow
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
Miodrag Milanović
910f421324
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
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anlogic: Use dfflegalize.
2020-07-16 18:07:58 +02:00
clairexen
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
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Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
Marcelina Kościelnicka
3050454d6e
anlogic: Use dfflegalize.
2020-07-14 05:02:50 +02:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
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This reverts commit 09ecb9b2cf
.
2020-07-13 18:05:38 +02:00
Marcelina Kościelnicka
347dd01c2f
xilinx: Fix srl regression.
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Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
Kamil Rakoczy
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
.
2020-07-10 09:59:48 +02:00
whitequark
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9
.
This reverts commit b422f2e4d0
.
This reverts commit 7cb56f34b0
.
This reverts commit 6f9be939bd
.
This reverts commit 76a34dc5f3
.
2020-07-09 19:36:32 +00:00
Marcelina Kościelnicka
7ed9d18907
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka
32d2cc8c28
clkbufmap: improve input pad handling.
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- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
2020-07-09 18:48:01 +02:00
clairexen
802671b22e
Merge pull request #2244 from antmicro/logic
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Add logic type support to parameters
2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka
03e28f7ab4
clk2fflogic: Consistently treat async control signals as negative hold.
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This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717
dfflegalize: Add special support for const-D latches.
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Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
Kamil Rakoczy
b422f2e4d0
Add logic param and integer bad syntax tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-06 09:18:48 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
7f45cab27a
synth_gowin: ABC9 support
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This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
Dan Ravensloft
0d4c2f0a65
intel_alm: add Cyclone 10 GX tests
2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka
7afcb72c98
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
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Fixes #2221 .
2020-07-05 06:31:58 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd
Improve MISTRAL_FF specify rules
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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07
tests: update fsm.ys resource count
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Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862 ?
2020-07-04 19:45:10 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
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Add dfflegalize pass.
2020-07-02 17:46:11 +02:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
Marcelina Kościelnicka
6b42819a37
dfflegalize: Add tests.
2020-07-01 01:57:15 +02:00
Zachary Snow
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
Kamil Rakoczy
76a34dc5f3
Add signed/unsigned tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:38:20 +02:00
Kamil Rakoczy
39c39848a2
Add sub-assign and and-assign tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:32:05 +02:00
Kamil Rakoczy
470df03f3d
Move combined assign tests to single file
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 14:19:16 +02:00
Kamil Rakoczy
f6d06c9f7b
Add xor-assignment test
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 14:46:21 +02:00
Kamil Rakoczy
a5ca4eeefb
Add or-assignment and plus-assignment tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:56:26 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Kazuki Sakamoto
6bf75be73b
static cast: add tests
2020-06-19 17:40:38 -07:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
diego
d68a8f9e2b
Removing trailing whitespace
2020-06-10 10:35:40 -05:00
Claire Wolf
b3b515087d
Fix tests/opt/opt_rmdff
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This only passed before because "prep" was also running opt_rmdff
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
diego
3c2a1171ff
Adding latch tests for shift&mask AST dynamic part-select enhancements
2020-06-09 15:17:01 -05:00
Peter Crozier
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
Claire Wolf
7112f187cd
Add missing .gitignore file
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
Eddie Hung
8a11019d38
tests: tidy up testcase
2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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tests: reduce test warnings
2020-06-03 08:37:07 -07:00
Miodrag Milanovic
0a88f002e5
allow range for mux test
2020-06-01 13:48:19 +02:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
Xiretza
6a2bac21d3
Expand tests/simple/constmuldivmod.v
2020-05-28 22:59:04 +02:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs
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Add `printattrs` command to print attributes of currently selected objects.
2020-05-28 10:25:34 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test.
2020-05-27 08:00:00 +00:00
Eddie Hung
1dce798dc5
tests: add ecp5 latch testcase with -abc9
2020-05-25 16:39:16 -07:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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xilinx: tidy up cells_sim.v a little
2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1
tests: xilinx macc test to have initval, shorten BMC depth for runtime
2020-05-25 10:09:05 -07:00
Eddie Hung
60aa804915
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
Eddie Hung
9c6d216a06
tests: add test for abc9 -dff removing a redundant flop entirely
2020-05-25 08:43:33 -07:00
Eddie Hung
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
Eddie Hung
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
Eddie Hung
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Eddie Hung
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
Eddie Hung
5ad3a85288
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
Eddie Hung
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
Eddie Hung
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
Eddie Hung
49e64ad492
test: update opt_expr_alu test
2020-05-08 11:12:58 -07:00
Eddie Hung
495acf9815
tests: opt_expr tests that depend on consumex
2020-05-08 11:07:11 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
...
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
Eddie Hung
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
Eddie Hung
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
Claire Wolf
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
Eddie Hung
7f203cb019
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
Eddie Hung
b5f38f8342
opt_expr: const_xnor replacement to pad Y with 1'b1
2020-04-24 14:13:45 -07:00
Eddie Hung
ebd6fa945d
tests: opt_expr update xnor/xor tests
2020-04-24 11:16:25 -07:00
Eddie Hung
90b71eb84b
opt_expr: do not group by X, more fixes
2020-04-23 18:15:07 -07:00
Eddie Hung
b84415094c
tests: add opt_expr tests
2020-04-23 15:58:36 -07:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Eddie Hung
988d47af85
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
Eddie Hung
db09e96dff
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
Eddie Hung
f582eb14af
xilinx: xilinx_dffopt to read cells_sim.v; fix test
2020-04-22 16:25:23 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
Eddie Hung
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966
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tests: fix various/plugin.sh when PREFIX != /usr/local/share
2020-04-22 10:19:30 -07:00
Eddie Hung
281cd10717
tests: update select black/white-box tests
2020-04-22 10:16:14 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
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design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
Eddie Hung
634b5e2d9f
tests: use `yosys-config --datdir` instead of hard-coded
2020-04-22 08:29:45 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
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sim: Fix handling of constant-connected cell inputs at startup
2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
846c79b312
hierarchy: Convert positional parameters to named.
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Fixes #1821 .
2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
David Shah
abf81c7639
sim: Fix handling of constant-connected cell inputs at startup
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-21 08:58:52 +01:00
Eddie Hung
38ee59184c
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
Eddie Hung
caf4071c8b
Remove '-ignore_unknown_cells' option from 'sat'
2020-04-20 11:58:23 -07:00
Eddie Hung
a1573058e9
Simplify test case script
2020-04-20 11:54:10 -07:00
Eddie Hung
99a0958601
Remove ununsed files
2020-04-20 11:53:48 -07:00
diego
22f440506b
Modifications of tests as per Eddie's request
2020-04-20 12:45:35 -05:00
Eddie Hung
34d8ff8b56
abc9: add testcase reduced from #1970
2020-04-20 09:38:29 -07:00
diego
50581d5a94
Wrong fixed value
2020-04-17 10:15:22 -05:00
Eddie Hung
9eace8f360
design: add test
2020-04-16 12:48:40 -07:00
Eddie Hung
2ddfb61e65
select: add test for not selecting inside black/white boxes
2020-04-16 12:45:04 -07:00
diego
87910732f1
Adding tests for dynamic part select optimisation
2020-04-16 13:31:05 -05:00
Eddie Hung
2623e335cc
tests: add select -unset tests
2020-04-16 10:51:58 -07:00
Eddie Hung
e8a841467f
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
David Shah
2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919
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ast: Fix handling of identifiers in the global scope
2020-04-16 13:48:20 +01:00
Marcelina Kościelnicka
2f8541a92e
opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
2020-04-16 11:48:29 +02:00
David Shah
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
Eddie Hung
33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
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zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
Claire Wolf
4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876
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Fix handling of ternary with constant condition
2020-04-15 16:01:19 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
Eddie Hung
383fe4a4bc
tests: zinit for new types
2020-04-14 13:08:37 -07:00
Marcelina Kościelnicka
6c16fd760b
opt_expr: Add more $alu optimizations.
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Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.
Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).
Fixes #1912 .
2020-04-14 21:48:13 +02:00
Eddie Hung
e7121cc15c
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
Marcelina Kościelnicka
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
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Fixes #1704 .
2020-04-14 19:52:19 +02:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
Eddie Hung
b75c5bf743
zinit: resolve one more comment by @mwkmwkmwk
2020-04-13 15:25:37 -07:00
Eddie Hung
c6afce7638
zinit: fix review comments from @mwkmwkmwk
2020-04-13 15:16:51 -07:00
Eddie Hung
091297b9ee
tests: zinit on $adff
2020-04-13 14:29:44 -07:00
Eddie Hung
3c5a9411b1
Add testcase for $_DFF_[NP][NP][01]_
2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka
840bb17089
opt_expr: Optimize multiplications with low 0 bits in operands.
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Fixes #1500 .
2020-04-13 16:52:22 +02:00
Xiretza
7f1d83c5db
Add .gitignore to tests/select/
2020-04-12 22:45:45 +02:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style
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ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
2020-04-10 14:51:01 +00:00
Eddie Hung
f11dd6e208
tests: add a quick plugin test
2020-04-09 09:45:20 -07:00
Jeff Wang
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
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"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
Eddie Hung
92d70cafec
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
2020-04-03 14:28:22 -07:00
whitequark
763401fc82
ecp5: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
whitequark
ebee746ad2
ice40: do not map FFRAM if explicitly requested otherwise.
2020-04-03 05:51:40 +00:00
Marcin Kościelnicki
2d3753d730
iopadmap: Fix z assignment to inout port
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Fixes #1841 .
2020-04-02 18:15:04 +02:00
Eddie Hung
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
Eddie Hung
e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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opt_expr: improve performance on $alu and $sub
2020-04-01 14:11:09 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
Eddie Hung
1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
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opt_merge: speedup
2020-03-31 14:50:32 -07:00
Eddie Hung
3df66027e0
Add dynamic slicing Verilog testcase
2020-03-31 11:51:31 -07:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Claire Wolf
590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
2020-03-26 19:03:37 +01:00
Peter Crozier
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
N. Engelhardt
3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
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Closes #1762 . Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
Alberto Gonzalez
0da65d498b
Do not warn on empty selection with prefixed `arg_memb`.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-23 17:50:11 +00:00
Alberto Gonzalez
ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set.
2020-03-23 17:30:53 +00:00
Alberto Gonzalez
1b333d49ef
Add tests for `select` command warnings.
2020-03-23 17:30:53 +00:00
N. Engelhardt
b86905d952
Merge pull request #1803 from Grazfather/typedef
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Support standard typedef grammar (Fixed)
2020-03-23 13:43:35 +01:00
Marcin Kościelnicki
c2bf11e42a
techmap: Fix cell names with _TECHMAP_REPLACE_.*
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Fixes #1804 .
2020-03-23 11:17:07 +01:00
Peter
6d8d6b402f
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
Eddie Hung
6274f0b075
opt_expr: add failing $xnor test
2020-03-20 14:38:50 -07:00
David Shah
fa77fb857b
Add test for abc9+mince issue
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:35:28 +00:00
Eddie Hung
317c18fc6f
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
Eddie Hung
81ca776ea4
opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
2020-03-19 16:59:11 -07:00
Eddie Hung
5e2562f1a2
opt_expr: add $alu tests
2020-03-19 14:57:10 -07:00
Marcin Kościelnicki
e91368a5f4
fsm_extract: Initialize celltypes with full design.
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Fixes #1781 .
2020-03-19 18:51:21 +01:00
N. Engelhardt
e03f725ef2
Merge pull request #1774 from boqwxp/exec
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Add `exec` command to allow running shell commands from inside Yosys scripts
2020-03-19 13:14:43 +01:00
N. Engelhardt
644deb708d
fix argument order for macOS compatibility
2020-03-18 15:11:49 +01:00
Eddie Hung
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
Alberto Gonzalez
a09b260c01
Add test for `exec` command.
2020-03-16 07:52:58 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Marcus Comstedt
dd562f29e7
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
Miodrag Milanovic
5b73e7c63a
Added back tests for logger
2020-03-13 15:00:18 +01:00
Eddie Hung
3ada82639f
verilog: add test
2020-03-11 06:51:03 -07:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
N. Engelhardt
88494e81f5
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
Eddie Hung
3c2e910bb3
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
David Shah
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
Eddie Hung
a179d918ec
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
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This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
2020-02-27 10:17:29 -08:00
Eddie Hung
f858219c4e
Cleanup tests
2020-02-27 10:17:29 -08:00
Eddie Hung
717fb492b3
Update bug1630.ys to use -lut 4 instead of lut file
2020-02-27 10:17:29 -08:00
Eddie Hung
bc97e64b21
Fix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 10:17:29 -08:00
Eddie Hung
977262c803
Update simple_abc9 tests
2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
Alberto Gonzalez
2c2f092c90
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Marcin Kościelnicki
cd60f079d6
tests/aiger: Add missing .gitignore
2020-02-15 19:52:21 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test
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make rpc frontend unix socket test less fragile
2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55
make rpc frontend unix socket test less fragile
2020-02-13 20:52:22 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master
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$readmem[hb] file inclusion is now relative to the Verilog file
2020-02-10 08:31:01 -08:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
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There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
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LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
...
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
whitequark
29d130dee9
ice40: remove impossible test.
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iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e
, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo
9da5936c05
Added 'set -e' into tests/memfile/run-test.sh
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Also added two checks for situations where the execution must fail.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:45:40 -03:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
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techmap LSB-first for compatible $shift/$shiftx cells
2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Stefan Biereigel
90c78f1f85
add testcase for #1614
2020-02-03 21:29:54 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master
2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
David Shah
ebe1d7d5ab
sv: More tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
a210675d71
sv: Add tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7
Removed 'synth' into tests/memfile/run-test.sh
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46
Added content1.dat into tests/memfile
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Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
eaaba6e091
Added tests/memfile to 'make test' with an extra testcase
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c
Added a test for the Memory Content File inclusion using $readmemb
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:41:10 -03:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix
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Fix for non-deterministic test
2020-01-29 11:18:06 +01:00
Eddie Hung
d004953772
Add "help -all" and "help -celltypes" sanity test
2020-01-28 18:11:34 -08:00
Eddie Hung
a855f23f22
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Miodrag Milanovic
94191a93dd
Updated test to use assert-max
2020-01-28 18:26:10 +01:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
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sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-27 09:54:04 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
2d795fb8c0
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 22:07:43 -08:00
Eddie Hung
dca1c806ec
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 19:55:11 -08:00
Eddie Hung
e471b330ac
abc_box_id -> abc9_box_id in test
2020-01-23 19:12:19 -08:00
Eddie Hung
11e50c0e9e
Test for (* keep *)-ed abc9_box_id
2020-01-23 18:56:25 -08:00
Eddie Hung
48aec34e0d
abc_box_id -> abc9_box_id in test
2020-01-23 18:53:14 -08:00
Eddie Hung
5aaa19f1ab
Update tests with reduced area
2020-01-21 16:50:04 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Jeff Wang
8ef5c7d48c
scoped enum tests
2020-01-16 18:13:30 -05:00