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Add xor-assignment test 

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-24 14:38:03 +02:00
parent a4b4c22c96
commit f6d06c9f7b
1 changed files with 15 additions and 0 deletions
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tests/opt/opt_expr_xor_assignment.ys Normal file
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read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a ^= i;
a ^= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i