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verlog: allow shadowing module ports within generate blocks 

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
This commit is contained in:
Zachary Snow 2021-02-06 23:54:17 -05:00
parent eff18a2b15
commit 1d5f3fe506
3 changed files with 29 additions and 4 deletions
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11
frontends/verilog/verilog_parser.y
View File

@ -1784,7 +1784,13 @@ wire_name:
}
rewriteAsMemoryNode(node, $2);
}
if (current_function_or_task == NULL) {
if (current_function_or_task) {
if (node->is_input || node->is_output)
node->port_id = current_function_or_task_port_id++;
} else if (ast_stack.back()->type == AST_GENBLOCK) {
if (node->is_input || node->is_output)
frontend_verilog_yyerror("Cannot declare module port `%s' within a generate block.", $1->c_str());
} else {
if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
port_stubs[*$1] = ++port_counter;
}
@ -1799,9 +1805,6 @@ wire_name:
if (node->is_input || node->is_output)
frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
}
} else {
if (node->is_input || node->is_output)
node->port_id = current_function_or_task_port_id++;
}
//FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
SET_AST_NODE_LOC(node, @1, @1);

10
tests/simple/genblk_port_shadow.v Normal file
View File

@ -0,0 +1,10 @@
module top(x);
generate
if (1) begin : blk
wire x;
assign x = 0;
end
endgenerate
output wire x;
assign x = blk.x;
endmodule

12
tests/verilog/genblk_port_decl.ys Normal file
View File

@ -0,0 +1,12 @@
logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
read_verilog <<EOT
module top(x);
generate
if (1) begin : blk
output wire x;
assign x = 1;
end
endgenerate
output wire x;
endmodule
EOT