tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
091bbd4d9c
|
start refactoring the num_config_bits for circuit model
|
2019-09-26 22:53:07 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |
|
tangxifan
|
f0589cc2cf
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
|
tangxifan
|
05eaa412b1
|
refactored short-connection of switch block
|
2019-09-26 14:31:05 -06:00 |
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
tangxifan
|
ea0da49e04
|
Merge branch 'dev' into refactoring
|
2019-09-25 21:06:06 -06:00 |
|
tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
|
2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
|
2019-09-23 20:25:53 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
|
2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
1e4177067d
|
remove port size in the module definition
|
2019-09-22 11:21:43 -06:00 |
|
tangxifan
|
0ff0c8cf06
|
bug fix for IO=1
|
2019-09-19 15:43:25 -06:00 |
|
tangxifan
|
e0b253d30a
|
minor fix for non-LUT intermedate buffer case
|
2019-09-18 15:15:03 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
2294aecef2
|
remove old codes and compact new codes
|
2019-09-16 20:19:14 -06:00 |
|
tangxifan
|
c5ee81541a
|
remove dead codes in routing module generation
|
2019-09-16 18:47:01 -06:00 |
|
tangxifan
|
0963852091
|
remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
|
2019-09-16 18:38:37 -06:00 |
|
tangxifan
|
d83cad7c2e
|
refactoring Verilog generation for routing channels
|
2019-09-16 17:35:51 -06:00 |
Baudouin Chauviere
|
d5ebe66ad9
|
Bug fix
|
2019-09-16 10:57:52 -06:00 |
Ganesh Gore
|
d90329678a
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-09-14 12:11:36 -06:00 |
|
Ganesh Gore
|
ec3854a648
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-14 00:14:17 -06:00 |
|
tangxifan
|
f69ce708ca
|
rework on the order of top-level functions
|
2019-09-13 21:59:52 -06:00 |
|
tangxifan
|
29e80d157c
|
Start developing BitstreamContext
|
2019-09-13 21:27:47 -06:00 |
|
tangxifan
|
e64cfc5852
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
Baudouin Chauviere
|
737cfb1086
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-09-13 16:02:06 -06:00 |
|
Baudouin Chauviere
|
63e6ed21b5
|
Fully functional
|
2019-09-13 16:02:06 -06:00 |
|
tangxifan
|
d6fc9c1c71
|
Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
|
2019-09-13 15:36:35 -06:00 |
|
tangxifan
|
009c0d63b5
|
refactored the memory bank. Ready to plug-in the test
|
2019-09-13 15:05:31 -06:00 |
|
tangxifan
|
99c30fa7dd
|
keep refactoring the memory Verilog generation
|
2019-09-13 14:02:04 -06:00 |
|
tangxifan
|
56f40cf46c
|
light modification on Verilog Mux generation and start refactoring memory Verilog generation
|
2019-09-13 12:22:57 -06:00 |
|
tangxifan
|
d8b9349066
|
remove legacy codes
|
2019-09-13 11:48:25 -06:00 |
|
tangxifan
|
b920f0fc38
|
refactored user template Verilog generation
|
2019-09-13 11:41:54 -06:00 |
|
tangxifan
|
0e6c88dd52
|
delete legacy codes for wire Verilog generation
|
2019-09-12 21:06:53 -06:00 |
|
tangxifan
|
c20e182484
|
plugged in the refactored wire Verilog generation
|
2019-09-12 20:56:30 -06:00 |
|
tangxifan
|
2b829238b5
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
tangxifan
|
79fa858f36
|
remove unused ports for Verilog modules
|
2019-09-11 19:39:59 -06:00 |
|
tangxifan
|
2bed51bf29
|
minor bug fix for echo
|
2019-09-11 17:41:45 -06:00 |
|
tangxifan
|
0399319212
|
refactored LUT Verilog generation
|
2019-09-11 17:04:43 -06:00 |
|
tangxifan
|
6a5b50facf
|
refactored RRAM MUX verilog generation
|
2019-09-10 20:45:44 -06:00 |
|
tangxifan
|
0711aa1bd6
|
minor bug fixing
|
2019-09-10 16:56:14 -06:00 |
|
tangxifan
|
82683d49cf
|
remove legacy codes of local encoders
|
2019-09-10 15:34:20 -06:00 |
|
tangxifan
|
5f561ef5e3
|
pass regression test when plug in refactored local encoders
|
2019-09-10 15:26:47 -06:00 |
|
tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
|
2019-09-10 15:16:29 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
tangxifan
|
59edd49862
|
refactored CMOS MUX buffering
|
2019-09-06 16:39:34 -06:00 |
|
tangxifan
|
bc9d95408e
|
bug fixed and refactored intermediate buffer addition
|
2019-09-05 16:09:28 -06:00 |
|
tangxifan
|
e623c19055
|
implementing mux Verilog generation. Bugs detected, fixing ongoing
|
2019-09-04 23:54:53 -06:00 |
|
tangxifan
|
fde9c8b4ec
|
add frac_lut outputs to mux_graph generation
|
2019-09-03 23:19:24 -06:00 |
|
tangxifan
|
b6bb433edc
|
bug fixing for datapath mux size in Verilog generation
|
2019-09-03 18:09:21 -06:00 |
|
tangxifan
|
4d183a3fe4
|
start developing mux Verilog module generation
|
2019-09-03 16:59:03 -06:00 |
|
tangxifan
|
a8c803f08f
|
try to fix bugs in explicit port mapping
|
2019-09-02 16:37:43 -06:00 |
|
tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
|
2019-09-02 16:21:29 -06:00 |
|
tangxifan
|
395bf4fbdf
|
refactored rram mux generation
|
2019-09-02 14:30:18 -06:00 |
|
tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
|
2019-08-27 18:39:25 -06:00 |
|
tangxifan
|
ab6f1a5461
|
add mux output ids for mux_graph
|
2019-08-26 21:21:50 -06:00 |
|
tangxifan
|
b6617a5adf
|
fix bugs in verilog comment lines
|
2019-08-25 16:37:46 -06:00 |
|
tangxifan
|
14db2bf1a9
|
minor fixing on comment
|
2019-08-25 16:35:49 -06:00 |
|
tangxifan
|
706b7f3427
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-25 15:52:04 -06:00 |
|
tangxifan
|
1cfc117b32
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 15:47:57 -06:00 |
|
tangxifan
|
056c45321b
|
plug in module manager
|
2019-08-25 15:44:31 -06:00 |
|
tangxifan
|
8fc258cc93
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-25 15:33:37 -06:00 |
|
tangxifan
|
c43fabb43c
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 10:31:45 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
|
2019-08-23 16:36:30 -06:00 |
|
tangxifan
|
931b042750
|
refactoring module manager
|
2019-08-23 12:52:01 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
|
2019-08-22 23:49:35 -06:00 |
|
tangxifan
|
3f45e6cc87
|
remove dead codes for essential gates code generation
|
2019-08-22 10:01:52 -06:00 |
|
tangxifan
|
43de2d7636
|
some tuning on Verilog port formatting
|
2019-08-21 23:47:50 -06:00 |
|
tangxifan
|
1be5632e92
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
tangxifan
|
7b0c55ce15
|
try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
|
2019-08-21 22:45:48 -06:00 |
|
tangxifan
|
5a40c6713d
|
managed to plug in refactored essential gates, dead codes to be removed
|
2019-08-21 21:50:26 -06:00 |
|
tangxifan
|
d8eb9866a0
|
refactored gate verilog generation
|
2019-08-21 18:49:48 -06:00 |
|
tangxifan
|
b08ff465c9
|
refactored pass-gate verilog generation
|
2019-08-21 17:33:16 -06:00 |
|
tangxifan
|
5e156dc725
|
minor fix for OSX and update travis using ccache to speed up compilation
|
2019-08-21 15:25:36 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
|
2019-08-20 21:56:55 -06:00 |
|
tangxifan
|
19472ace4e
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
bee070d7cc
|
start plug in MUX library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
893683fa95
|
start developing mux library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
153d506abb
|
add graph-based mux decoding function
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
dcca9f4f0f
|
finish mux graph builders
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
638969c3c9
|
adding mux graph data structures
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
0b8473e960
|
start developing graphs for muxes, with aims to simplify netlist and bitstream generation
|
2019-08-20 15:24:52 -06:00 |
|
Ganesh Gore
|
69ffc38645
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-19 21:59:06 -06:00 |
|
Ganesh Gore
|
7bfc48b8e4
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
|
tangxifan
|
e456b6f905
|
replace spice_models with circuit model in bitstream generator
|
2019-08-16 16:36:49 -06:00 |
|
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
|
tangxifan
|
b66e120366
|
patch on local encoders for unused configuration, avoid chip-burn issues
|
2019-08-16 15:32:23 -06:00 |
|
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
|
AurelienUoU
|
8e38aa6019
|
Merge with heterogeneous for unfracturable LUT bug fix
|
2019-08-14 10:10:27 -06:00 |
|
AurelienUoU
|
df873903f8
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
|
AurelienUoU
|
30c0f2b6b7
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-14 09:11:54 -06:00 |
|
AurelienUoU
|
90aaed6e1f
|
Fix regression test
|
2019-08-14 09:10:13 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
|
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
|
2019-08-13 15:37:42 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
AurelienUoU
|
8dab4dec90
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-13 11:09:29 -06:00 |
|
AurelienUoU
|
7851246424
|
Resolve merge issue
|
2019-08-13 11:08:30 -06:00 |
|
AurelienUoU
|
2da4d3f33c
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-12 09:57:02 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
|
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
AurelienUoU
|
40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-29 11:45:23 -06:00 |
|
tangxifan
|
32e3a556b9
|
bug fixing herited from explicit mapping
|
2019-07-17 09:26:05 -06:00 |
|
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
|
2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
|
2019-07-17 08:36:09 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
|
2019-07-17 07:54:23 -06:00 |
|
tangxifan
|
e9154b1f74
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 14:42:45 -06:00 |
|
tangxifan
|
115411941b
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 13:15:45 -06:00 |
|
Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
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e602006a07
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-16 12:45:13 -06:00 |
|
AurelienUoU
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b810b5cab9
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fpga_flow bug fix + upload k8 architecture
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2019-07-16 07:04:45 -06:00 |
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AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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tangxifan
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bcc6346533
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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tangxifan
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4c6e245885
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speed-up the unique routing process
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2019-07-14 12:22:00 -06:00 |
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tangxifan
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b690e702f6
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adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
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tangxifan
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aa4cd850ae
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try to optimize the runtime of routing uniqueness detection
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2019-07-13 18:10:34 -06:00 |
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tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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AurelienUoU
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ef600bc63f
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Save workspace
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2019-07-12 15:57:41 -06:00 |
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Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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tangxifan
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cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
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2019-07-11 21:02:09 -06:00 |
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Baudouin Chauviere
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c9b84f61c9
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Hot fix
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2019-07-11 17:39:02 -06:00 |
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Baudouin Chauviere
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d0cd5a2bc1
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Hot fix
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2019-07-11 17:27:31 -06:00 |
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tangxifan
|
9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
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Baudouin Chauviere
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f4be375637
|
Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
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tangxifan
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a90316e9f4
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
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tangxifan
|
acee0161c7
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Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
|
Baudouin Chauviere
|
6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
|
Baudouin Chauviere
|
0a978db866
|
Fix regression test
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2019-07-10 14:16:34 -06:00 |
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tangxifan
|
b7f9831bd2
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add statistics for unique GSBs
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2019-07-10 13:08:03 -06:00 |
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tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
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2019-07-10 12:05:43 -06:00 |
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tangxifan
|
57ae5dbbec
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bug fixing for rectangle FPGA sizes
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2019-07-09 20:47:52 -06:00 |
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tangxifan
|
edfe3144c3
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update profiling, found where runtime is lost
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2019-07-09 20:28:01 -06:00 |
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tangxifan
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737cc2874f
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Merge branch 'tileable_routing' into dev
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2019-07-09 17:42:44 -06:00 |
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tangxifan
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65f696c1d7
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fix critical bugs in rectangle floorplan
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2019-07-09 17:41:20 -06:00 |
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Baudouin Chauviere
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4ca0967453
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-09 14:35:51 -06:00 |
|
Baudouin Chauviere
|
792ba23f4f
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Correction pre-merge
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2019-07-09 14:34:34 -06:00 |
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Baudouin Chauviere
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589f58b55e
|
Regression test succeeded
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2019-07-09 09:18:06 -06:00 |
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Baudouin Chauviere
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25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
tangxifan
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5d5e09fcdb
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minor fix in trying to accelerate the unique routing functions
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2019-07-08 17:12:36 -06:00 |
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Baudouin Chauviere
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df0a3d23a3
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Correction top module
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2019-07-08 10:23:14 -06:00 |
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Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
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tangxifan
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76fefdb876
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bug fixing in Fc_in and be serious in the performance of rr_graph
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2019-07-05 16:23:15 -06:00 |
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tangxifan
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c62762ce59
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bug fixing in assign ipins to tracks using Fc_in
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2019-07-05 13:42:22 -06:00 |
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tangxifan
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64d8e9663a
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minor fix to satisfy Fc_in and Fc_out
|
2019-07-05 13:13:35 -06:00 |
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tangxifan
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3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
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d64aeef5c4
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add profiling to routing compact process
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2019-07-03 16:57:34 -06:00 |
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tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
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2019-07-03 16:46:43 -06:00 |
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tangxifan
|
b79d276ea9
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add profiling to fpga_x2p_setup
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2019-07-03 14:44:54 -06:00 |
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tangxifan
|
d5137eb424
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-03 14:31:18 -06:00 |
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tangxifan
|
5195faab8b
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:30:39 -06:00 |
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tangxifan
|
4f3cb0bdf3
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added tileable routing chanW adaption to fixed W router
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2019-07-03 14:29:50 -06:00 |
|
Ganesh Gore
|
443a73954f
|
Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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Ganesh Gore
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57ad71438b
|
Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
|
2019-07-03 13:39:52 -06:00 |
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tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
|
2019-07-03 10:33:02 -06:00 |
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tangxifan
|
4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
|
2019-07-02 15:34:59 -06:00 |
|
Baudouin Chauviere
|
b08513d902
|
Big chunk added on the routing part of the explicit mapping
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2019-07-02 14:12:42 -06:00 |
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Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
|
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
|
tangxifan
|
44301bfd77
|
updated SPICE generator to avoid issues on clb2clb_direct
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2019-07-02 09:01:52 -06:00 |
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tangxifan
|
5b25bbb120
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bug fixed for direct connection in CBs and direct connection in top netlist
|
2019-07-01 17:25:00 -06:00 |
|
Baudouin Chauviere
|
f189ef1d8f
|
Done with the submodules
|
2019-07-01 14:24:09 -06:00 |
|
Baudouin Chauviere
|
370ce23646
|
Mux explicit verilog done
|
2019-07-01 13:58:24 -06:00 |
|
Baudouin Chauviere
|
863e8677c0
|
Further add new functions to tree
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2019-07-01 12:12:36 -06:00 |
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Baudouin Chauviere
|
0e04b88c8f
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
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tangxifan
|
1332ba62e8
|
update tileable rr_graph generator to improve routability and also enable assoicated testing
|
2019-06-27 17:52:25 -06:00 |
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tangxifan
|
15c536e9b4
|
minor fixing in printing the rr_node stats
|
2019-06-27 16:34:21 -06:00 |
|
Baudouin Chauviere
|
04eb6d3488
|
Correction pre-merge
|
2019-06-27 14:33:06 -06:00 |
|
Ganesh Gore
|
11e6350214
|
Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev
|
2019-06-27 14:22:40 -06:00 |
|
Baudouin Chauviere
|
7c742f1cbb
|
Stable, is_explicit propagated through the code. Not implemented though except for muxes
|
2019-06-27 10:29:57 -06:00 |
|
tangxifan
|
8edd85c9fc
|
keep fixing bugs in verilog SDC generator for tileable CBs
|
2019-06-26 22:58:52 -06:00 |
|
tangxifan
|
711e369fe7
|
fixing bugs in the SDC generator and report_timing
|
2019-06-26 18:09:09 -06:00 |
|
tangxifan
|
0fe54d87d5
|
fixed a bug in SDC generator for constraining SBs in tileable arch
|
2019-06-26 17:06:14 -06:00 |
|
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
|
tangxifan
|
7d85eb544d
|
start fixing bugs for SDC generator when using tileable arch
|
2019-06-26 16:48:17 -06:00 |
|
tangxifan
|
f5920c7422
|
fix bugs in ptc_num using for SB
|
2019-06-26 16:21:02 -06:00 |
|
tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
|
2019-06-26 15:51:11 -06:00 |
|
tangxifan
|
d2ed82d14d
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 15:00:39 -06:00 |
|
tangxifan
|
57616361c2
|
fixed critical bugs in cb configuration port indices
|
2019-06-26 14:58:52 -06:00 |
|
Baudouin Chauviere
|
d2bd2be76b
|
Warnings correction in the make sequence
|
2019-06-26 14:33:12 -06:00 |
|
Baudouin Chauviere
|
87ddca9f57
|
commiting current work. Stable but function not implemented yet
|
2019-06-26 14:22:02 -06:00 |
|
tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
|
2019-06-26 14:13:41 -06:00 |
|
tangxifan
|
9b6a4b39bb
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 11:36:08 -06:00 |
|
tangxifan
|
c879e7f6c5
|
fixed a critical bug when instanciating Connection blocks
|
2019-06-26 11:33:02 -06:00 |
|
Baudouin Chauviere
|
b7c2954b91
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-26 10:51:55 -06:00 |
|
Baudouin Chauviere
|
8f21a3b177
|
Memory leakage correction
|
2019-06-26 10:50:38 -06:00 |
|
tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
|
2019-06-26 10:50:23 -06:00 |
|
AurelienUoU
|
ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
|
tangxifan
|
a3670bb752
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-26 09:45:04 -06:00 |
|
Baudouin Chauviere
|
56557b94e7
|
Bug Fix
|
2019-06-26 08:53:46 -06:00 |
|
tangxifan
|
3c0ef2067d
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
|
Baudouin Chauviere
|
bb250ddef9
|
Bug fix in cpp
|
2019-06-25 16:47:10 -06:00 |
|
Ganesh Gore
|
6d3066174b
|
Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev
|
2019-06-25 15:12:13 -06:00 |
|
tangxifan
|
4d3b5f12b4
|
fixed bugs for UNIVERSAL and WILTON switch blocks
|
2019-06-25 14:15:29 -06:00 |
|
Baudouin Chauviere
|
332ce17f03
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
|
tangxifan
|
a88263a4c2
|
update rr_block writer to include IPINs in XML files
|
2019-06-25 11:17:22 -06:00 |
|
tangxifan
|
785b560bd5
|
sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
|
2019-06-24 22:46:56 -06:00 |
|
tangxifan
|
fd301eeb66
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
|
tangxifan
|
0d62661c71
|
bug fixing and spot critical bugs in directlist parser
|
2019-06-23 20:52:38 -06:00 |
|
tangxifan
|
cdd4af9c58
|
vpr likes the tileable rr_graph while fpga_x2p does not
|
2019-06-23 18:11:13 -06:00 |
|
tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
|
tangxifan
|
2837f44df2
|
bug fixing for tileable rr_graph generator.
|
2019-06-22 20:41:06 -06:00 |
|
tangxifan
|
7c38b32eb1
|
keep bug fixing for tileable rr_graph generator
|
2019-06-21 22:51:11 -06:00 |
|
tangxifan
|
1b91c32121
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-21 17:59:55 -06:00 |
|
tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
|
AurelienUoU
|
0a42f6a796
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-21 15:47:14 -06:00 |