remove port size in the module definition

This commit is contained in:
tangxifan 2019-09-22 11:21:43 -06:00
parent 5efea159c5
commit 1e4177067d
1 changed files with 2 additions and 2 deletions

View File

@ -105,8 +105,8 @@ void print_verilog_module_definition(std::fstream& fp,
std::string port_whitespace(module_head_line.length(), ' ');
fp << port_whitespace;
}
/* Print port */
fp << generate_verilog_port(kv.second, port);
/* Print port: only the port name is enough */
fp << port.get_name();
port_cnt++;
}
}