remove port size in the module definition
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5efea159c5
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@ -105,8 +105,8 @@ void print_verilog_module_definition(std::fstream& fp,
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std::string port_whitespace(module_head_line.length(), ' ');
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fp << port_whitespace;
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}
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/* Print port */
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fp << generate_verilog_port(kv.second, port);
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/* Print port: only the port name is enough */
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fp << port.get_name();
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port_cnt++;
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}
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}
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