refactored short-connection of switch block
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@ -2145,6 +2145,157 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf
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return;
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}
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/*********************************************************************
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* Generate a port for a routing track of a swtich block
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********************************************************************/
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static
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BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb,
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const e_side& chan_side,
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t_rr_node* cur_rr_node,
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const PORTS& cur_rr_node_direction) {
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/* Get the index in sb_info of cur_rr_node */
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int index = rr_sb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction);
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/* Make sure this node is included in this sb_info */
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VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side));
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DeviceCoordinator chan_rr_node_coordinator = rr_sb.get_side_block_coordinator(chan_side);
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vtr::Point<size_t> chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y());
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std::string chan_port_name = generate_routing_track_port_name(rr_sb.get_chan_node(chan_side, index)->type,
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chan_port_coord, index,
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rr_sb.get_chan_node_direction(chan_side, index));
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return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */
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}
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/*********************************************************************
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* Print a short interconneciton in switch box
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* There are two cases should be noticed.
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* 1. The actual fan-in of cur_rr_node is 0. In this case,
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the cur_rr_node need to be short connected to itself which is on the opposite side of this switch
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* 2. The actual fan-in of cur_rr_node is 0. In this case,
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* The cur_rr_node need to connected to the drive_rr_node
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********************************************************************/
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static
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void print_verilog_unique_switch_box_short_interc(std::fstream& fp,
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const RRGSB& rr_sb,
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const e_side& chan_side,
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t_rr_node* cur_rr_node,
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const size_t& actual_fan_in,
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t_rr_node* drive_rr_node) {
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/* Check the driver*/
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if (0 == actual_fan_in) {
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VTR_ASSERT(drive_rr_node == cur_rr_node);
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} else {
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VTR_ASSERT(1 == actual_fan_in);
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}
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/* Check the file handler*/
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check_file_handler(fp);
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/* Find the name of output port */
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BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT);
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/* Find the name of input port */
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BasicPort input_port;
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/* Generate the input port object */
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switch (drive_rr_node->type) {
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/* case SOURCE: */
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case OPIN: {
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/* Find the coordinator (grid_x and grid_y) for the input port */
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vtr::Point<size_t> input_port_coord(drive_rr_node->xlow, drive_rr_node->ylow);
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std::string input_port_name = generate_grid_side_port_name(input_port_coord,
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rr_sb.get_opin_node_grid_side(drive_rr_node),
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drive_rr_node->ptc_num);
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input_port.set_name(input_port_name);
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input_port.set_width(1); /* Every grid output has a port size of 1 */
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break;
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}
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case CHANX:
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case CHANY: {
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enum e_side input_pin_side = chan_side;
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/* This should be an input in the data structure of RRGSB */
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if (cur_rr_node == drive_rr_node) {
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/* To be strict, the input should locate on the opposite side.
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* Use the else part if this may change in some architecture.
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*/
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Side side_manager(chan_side);
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input_pin_side = side_manager.get_opposite();
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} else {
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/* The input could be at any side of the switch block, find it */
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int index = -1;
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rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index);
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}
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/* We need to be sure that drive_rr_node is part of the SB */
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input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_pin_side, drive_rr_node, IN_PORT);
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break;
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}
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default: /* SOURCE, IPIN, SINK are invalid*/
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Print the wire connection in Verilog format */
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print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----"));
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print_verilog_wire_connection(fp, output_port, input_port, false);
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fp << std::endl;
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}
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/*********************************************************************
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* Print the Verilog modules for a interconnection inside switch block
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* The interconnection could be either a wire or a routing multiplexer,
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* which depends on the fan-in of the rr_nodes in the switch block
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********************************************************************/
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static
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void print_verilog_unique_switch_box_interc(ModuleManager& module_manager,
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std::fstream& fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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const RRGSB& rr_sb,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const std::vector<t_switch_inf>& rr_switches,
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const e_side& chan_side,
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const size_t& chan_node_id,
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const bool& use_explicit_mapping) {
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int num_drive_rr_nodes = 0;
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t_rr_node** drive_rr_nodes = NULL;
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/* Get the node */
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t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id);
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/* Determine if the interc lies inside a channel wire, that is interc between segments */
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/* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */
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if (true == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) {
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num_drive_rr_nodes = 0;
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drive_rr_nodes = NULL;
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} else {
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num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes;
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drive_rr_nodes = cur_rr_node->drive_rr_nodes;
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/* Special: if there are zero-driver nodes. We skip here */
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if (0 == num_drive_rr_nodes) {
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return;
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}
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}
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if (0 == num_drive_rr_nodes) {
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/* Print a special direct connection*/
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print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node,
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num_drive_rr_nodes, cur_rr_node);
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} else if (1 == num_drive_rr_nodes) {
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/* Print a direct connection*/
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print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node,
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num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]);
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} else if (1 < num_drive_rr_nodes) {
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/* Print the multiplexer, fan_in >= 2 */
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/*
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dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node,
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num_drive_rr_nodes, drive_rr_nodes,
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cur_rr_node->drive_switches[DEFAULT_SWITCH_ID],
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is_explicit_mapping);
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*/
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} /*Nothing should be done else*/
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}
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/*********************************************************************
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* Generate the Verilog module for a Switch Box.
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* A Switch Box module consists of following ports:
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@ -2338,6 +2489,19 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
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print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----"));
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/* TODO: Print routing multiplexers */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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print_verilog_comment(fp, std::string("----- " + side_manager.to_string() + " side Routing Multiplexers -----"));
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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/* We care INC_DIRECTION tracks at this side*/
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if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, rr_sb,
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circuit_lib, mux_lib, rr_switches,
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side_manager.get_side(),
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itrack, is_explicit_mapping);
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}
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}
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}
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_manager.module_name(module_id));
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