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some tuning on Verilog port formatting

This commit is contained in:
tangxifan 2019-08-21 23:47:50 -06:00
parent 1be5632e92
commit 43de2d7636
1 changed files with 4 additions and 0 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
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@ -107,6 +107,10 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
* others require a format of <port_type> [<lsb>:<msb>] <port_name>
*/
if (VERILOG_PORT_CONKT == verilog_port_type) {
/* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
if ( 1 == port_info.get_width()) {
size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
}
verilog_line = port_info.get_name() + size_str;
} else {
verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type];