some tuning on Verilog port formatting
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@ -107,6 +107,10 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
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* others require a format of <port_type> [<lsb>:<msb>] <port_name>
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*/
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if (VERILOG_PORT_CONKT == verilog_port_type) {
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/* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
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if ( 1 == port_info.get_width()) {
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size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
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}
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verilog_line = port_info.get_name() + size_str;
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} else {
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verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type];
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