From 43de2d7636675b7b3bba06f8130cc365de11c06d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 21 Aug 2019 23:47:50 -0600
Subject: [PATCH] some tuning on Verilog port formatting

---
 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
index ec8dae1a1..554579768 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
@@ -107,6 +107,10 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
    * others require a format of <port_type> [<lsb>:<msb>] <port_name> 
    */
   if (VERILOG_PORT_CONKT == verilog_port_type) {
+    /* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
+    if ( 1 == port_info.get_width()) {
+      size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
+    }
     verilog_line = port_info.get_name() + size_str;
   } else { 
     verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type];