Separated Modelsim tcl script generation
This commit is contained in:
Ganesh Gore
parent
bcbcd463fe
commit
d64bb18346
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@ -0,0 +1,8 @@
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read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} }
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set_top r:${SOURCE_TOP_DIR}
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read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} }
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set_top i:${IMPL_TOP_DIR}
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match
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${MATCH_MODUEL_LIST}
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verify
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@ -0,0 +1,86 @@
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from string import Template
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import sys
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import os
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import argparse
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import subprocess
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import logging
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from pprint import pprint
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configure logging system
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)10s) - %(message)s')
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logger = logging.getLogger('Modelsim_run_log')
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parser = argparse.ArgumentParser()
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parser.add_argument('files', nargs='+')
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parser.add_argument('--modelsim_template', type=str,
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help="Modelsim verification template file")
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parser.add_argument('--run_sim', action="store_true",
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help="Execute generated script in formality")
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args = parser.parse_args()
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if not args.modelsim_template:
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task_script_dir = os.path.dirname(os.path.abspath(__file__))
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args.modelsim_template = os.path.join(task_script_dir, os.pardir,
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"misc", "modelsim_template.j2")
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args.modelsim_template = os.path.abspath(args.modelsim_template)
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def main():
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for eachFile in args.files:
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eachFile = os.path.abspath(eachFile)
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directory = os.path.dirname(eachFile)
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os.chdir(directory)
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with open(eachFile, 'r') as fp:
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lines = fp.read().split("\n")
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SplitL = [indx for indx, eachL in enumerate(lines) if eachL == ""]
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SplitL = list(zip([0] + SplitL[:-1], SplitL))
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for indx, eachSection in enumerate(SplitL):
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SplitL[indx] = list(filter(None, lines[slice(*eachSection)]))
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match_str = "set_user_match r:%s i:%s -type port -noninverted"
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lables = {"SOURCE_DESIGN": " ".join(SplitL[0]),
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"SOURCE_TOP_DIR": "/WORK/" + " ".join(SplitL[1]),
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"IMPL_DESIGN": " ".join(SplitL[2]),
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"IMPL_TOP_DIR": "/WORK/" + " ".join(SplitL[3]),
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"MATCH_MODUEL_LIST": "\n".join([match_str % tuple(eachPort.split()) for eachPort in SplitL[4]])
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}
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tmpl = Template(open(args.modelsim_template, encoding='utf-8').read())
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with open("Output.tcl", 'w', encoding='utf-8') as tclout:
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tclout.write(tmpl.substitute(lables))
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if args.run_sim:
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formality_run_string = ["formality", "-file", "Output.tcl"]
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run_command("Modelsim run", "modelsim_run.log", formality_run_string)
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else:
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with open("Output.tcl", 'r', encoding='utf-8') as tclout:
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print(tclout.read())
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def run_command(taskname, logfile, command, exit_if_fail=True):
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logger.info("Launching %s " % taskname)
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with open(logfile, 'w+') as output:
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try:
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output.write(" ".join(command)+"\n")
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process = subprocess.run(command,
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check=True,
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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universal_newlines=True)
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output.write(process.stdout)
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if process.returncode:
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logger.error("%s run failed with returncode %d" %
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(taskname, process.returncode))
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except (Exception, subprocess.CalledProcessError) as e:
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logger.exception("failed to execute %s" % taskname)
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return None
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logger.info("%s is written in file %s" % (taskname, logfile))
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return process.stdout
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if __name__ == "__main__":
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main()
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@ -39,203 +39,217 @@
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#include "verilog_routing.h"
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#include "verilog_tcl_utils.h"
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static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){
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int i, j;
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// char* tmp = NULL;
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const t_pb_type *pb_type;
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t_mode *mode;
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t_pb_graph_node * node;
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// char* index = NULL;
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static void searching_used_latch(FILE *fp, t_pb *pb, int pb_index, char *chomped_circuit_name, char *inst_name)
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{
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int i, j;
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// char* tmp = NULL;
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const t_pb_type *pb_type;
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t_mode *mode;
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t_pb_graph_node *node;
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// char* index = NULL;
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pb_type = pb->pb_graph_node->pb_type;
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node = pb->pb_graph_node->physical_pb_graph_node;
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mode = &pb_type->modes[pb->mode];
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pb_type = pb->pb_graph_node->pb_type;
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node = pb->pb_graph_node->physical_pb_graph_node;
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mode = &pb_type->modes[pb->mode];
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// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index)))));
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// tmp = ff_hierarchy;
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// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_"));
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// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index)))));
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// tmp = ff_hierarchy;
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// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_"));
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if (pb_type->num_modes > 0) {
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for (i = 0; i < mode->num_pb_type_children; i++) {
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for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
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// if(strcmp(pb_type->name, mode->name) != 0)
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// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index)));
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if(pb->child_pbs[i][j].name != NULL)
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searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
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}
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}
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} else if((pb_type->class_type == LATCH_CLASS) && (pb->name)){
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// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_"))));
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fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name,
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pb->name,
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inst_name,
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gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node) );
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}
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//free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp
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return;
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if (pb_type->num_modes > 0)
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{
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for (i = 0; i < mode->num_pb_type_children; i++)
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{
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for (j = 0; j < mode->pb_type_children[i].num_pb; j++)
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{
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// if(strcmp(pb_type->name, mode->name) != 0)
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// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index)));
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if (pb->child_pbs[i][j].name != NULL)
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searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
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}
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}
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}
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else if ((pb_type->class_type == LATCH_CLASS) && (pb->name))
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{
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// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_"))));
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fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name,
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pb->name,
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inst_name,
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gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node));
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}
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//free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp
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return;
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}
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static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){
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t_pb* pb;
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char* inst_name = NULL;
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const t_pb_type *pb_type;
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t_mode *mode;
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int i, j, x_pos, y_pos;
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char* grid_x = NULL;
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char* grid_y = NULL;
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static void clb_iteration(FILE *fp, char *chomped_circuit_name, int h)
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{
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t_pb *pb;
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char *inst_name = NULL;
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const t_pb_type *pb_type;
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t_mode *mode;
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int i, j, x_pos, y_pos;
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char *grid_x = NULL;
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char *grid_y = NULL;
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x_pos = block[h].x;
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y_pos = block[h].y;
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x_pos = block[h].x;
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y_pos = block[h].y;
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pb = (t_pb*) block[h].pb;
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pb = (t_pb *)block[h].pb;
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pb_type = pb->pb_graph_node->pb_type;
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mode = &pb_type->modes[pb->mode];
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pb_type = pb->pb_graph_node->pb_type;
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mode = &pb_type->modes[pb->mode];
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grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_"));
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grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_"));
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grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_"));
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grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_"));
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if (strcmp(pb_type->name, FILL_TYPE->name) == 0) {
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inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid",my_strcat(grid_x, my_strcat(grid_y, "/" )))))));
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if (pb_type->num_modes > 0) {
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for (i = 0; i < mode->num_pb_type_children; i++) {
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inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_")))));
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for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
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/* If child pb is not used but routing is used, I must print things differently */
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if ((pb->child_pbs[i] != NULL)
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&& (pb->child_pbs[i][j].name != NULL)) {
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searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
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}
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}
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}
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}
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}
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return;
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if (strcmp(pb_type->name, FILL_TYPE->name) == 0)
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{
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inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid", my_strcat(grid_x, my_strcat(grid_y, "/")))))));
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if (pb_type->num_modes > 0)
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{
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for (i = 0; i < mode->num_pb_type_children; i++)
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{
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inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_")))));
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for (j = 0; j < mode->pb_type_children[i].num_pb; j++)
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{
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/* If child pb is not used but routing is used, I must print things differently */
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if ((pb->child_pbs[i] != NULL) && (pb->child_pbs[i][j].name != NULL))
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{
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searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
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}
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}
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}
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}
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}
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return;
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}
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static void match_registers(FILE *fp, char* chomped_circuit_name) {
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int h;
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for(h = 0; h < copy_nb_clusters; h++)
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clb_iteration(fp, chomped_circuit_name, h);
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/* for(h = 0; h < copy_nb_clusters; h++){
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free_cb(copy_clb[h].pb);
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free(copy_clb[h].name);
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free(copy_clb[h].nets);
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free(copy_clb[h].pb);
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}*/
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// free(copy_clb);
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// free(block);
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return;
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}
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static
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void formality_include_user_defined_verilog_netlists(FILE* fp,
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t_spice spice) {
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static void formality_include_user_defined_verilog_netlists(FILE *fp,
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t_spice spice)
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{
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int i;
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/* A valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s, [LINE%d])Invalid File Handler!\n",
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if (NULL == fp)
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{
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s, [LINE%d])Invalid File Handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Include user-defined sub-circuit netlist */
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for (i = 0; i < spice.num_include_netlist; i++) {
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if (0 == spice.include_netlists[i].included) {
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for (i = 0; i < spice.num_include_netlist; i++)
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{
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if (0 == spice.include_netlists[i].included)
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{
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assert(NULL != spice.include_netlists[i].path);
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fprintf(fp, "%s ", spice.include_netlists[i].path);
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fprintf(fp, "%s \n", spice.include_netlists[i].path);
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spice.include_netlists[i].included = 1;
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} else {
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}
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else
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{
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assert(1 == spice.include_netlists[i].included);
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}
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}
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}
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return;
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}
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void write_formality_script (t_syn_verilog_opts fpga_verilog_opts,
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char* fm_dir_formatted,
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char* src_dir_formatted,
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char* chomped_circuit_name,
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t_spice spice){
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int iblock;
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char* formality_script_file_name = NULL;
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char* benchmark_path = NULL;
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char* original_output_name = NULL;
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/* int output_length; */
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/* int pos; */
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FILE* fp = NULL;
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void write_formality_script(t_syn_verilog_opts fpga_verilog_opts,
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char *fm_dir_formatted,
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char *src_dir_formatted,
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char *chomped_circuit_name,
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t_spice spice)
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{
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int iblock, h;
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char *formScriptfp = NULL;
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char *benchmark_path = NULL;
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char *original_output_name = NULL;
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/* int output_length; */
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/* int pos; */
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FILE *fp = NULL;
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if(TRUE == fpga_verilog_opts.print_autocheck_top_testbench){
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if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench)
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{
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benchmark_path = fpga_verilog_opts.reference_verilog_benchmark_file;
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} else {
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}
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else
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{
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benchmark_path = "Insert verilog benchmark path";
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}
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formality_script_file_name = my_strcat(fm_dir_formatted, my_strcat(chomped_circuit_name, formality_script_name_postfix));
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fp = fopen(formality_script_file_name, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d])Failure in create formality script %s",
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__FILE__, __LINE__, formality_script_file_name);
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exit(1);
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}
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formScriptfp = my_strcat(fm_dir_formatted,
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my_strcat(chomped_circuit_name,
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formality_script_name_postfix));
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fp = fopen(formScriptfp, "w");
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if (NULL == fp)
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{
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d])Failure in create formality script %s",
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__FILE__, __LINE__, formScriptfp);
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exit(1);
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}
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/* Load Verilog benchmark as reference */
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fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path);
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fprintf(fp, "%s\n\n", benchmark_path);
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/* Set reference top */
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fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name);
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fprintf(fp, "%s\n\n", chomped_circuit_name);
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/* Load generated verilog as implemnetation */
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fprintf(fp, "read_verilog -container i -libname WORK -05 { ");
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fprintf(fp, "%s%s%s ", src_dir_formatted,
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chomped_circuit_name,
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verilog_top_postfix);
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fprintf(fp, "%s%s%s ", src_dir_formatted,
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chomped_circuit_name,
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formal_verification_verilog_file_postfix);
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fprintf(fp, "%s%s%s\n", src_dir_formatted, chomped_circuit_name,
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verilog_top_postfix);
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fprintf(fp, "%s%s%s\n", src_dir_formatted,
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chomped_circuit_name,
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formal_verification_verilog_file_postfix);
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init_include_user_defined_verilog_netlists(spice);
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formality_include_user_defined_verilog_netlists(fp, spice);
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fprintf(fp, "%s%s%s ", src_dir_formatted,
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default_rr_dir_name,
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routing_verilog_file_name);
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fprintf(fp, "%s%s%s ", src_dir_formatted,
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default_lb_dir_name,
|
||||
logic_block_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
default_submodule_dir_name,
|
||||
submodule_verilog_file_name);
|
||||
fprintf(fp, "}\n");
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_rr_dir_name,
|
||||
routing_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_lb_dir_name,
|
||||
logic_block_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_submodule_dir_name,
|
||||
submodule_verilog_file_name);
|
||||
fprintf(fp, "\n");
|
||||
|
||||
/* Set implementation top */
|
||||
fprintf(fp, "set_top i:/WORK/%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix));
|
||||
fprintf(fp, "%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix));
|
||||
/* Run matching */
|
||||
fprintf(fp, "match\n");
|
||||
fprintf(fp, "\n");
|
||||
/* Add manual matching for the outputs */
|
||||
for (iblock = 0; iblock < num_logical_blocks; iblock++) {
|
||||
for (iblock = 0; iblock < num_logical_blocks; iblock++)
|
||||
{
|
||||
original_output_name = NULL;
|
||||
if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) {
|
||||
if (iopad_verilog_model == logical_block[iblock].mapped_spice_model)
|
||||
{
|
||||
/* Make sure We find the correct logical block !*/
|
||||
assert((VPACK_INPAD == logical_block[iblock].type)
|
||||
||(VPACK_OUTPAD == logical_block[iblock].type));
|
||||
if(VPACK_OUTPAD == logical_block[iblock].type){
|
||||
assert((VPACK_INPAD == logical_block[iblock].type) || (VPACK_OUTPAD == logical_block[iblock].type));
|
||||
if (VPACK_OUTPAD == logical_block[iblock].type)
|
||||
{
|
||||
/* output_length = strlen(logical_block[iblock].name); */
|
||||
original_output_name = logical_block[iblock].name + 4;
|
||||
/* printf("%s", original_output_name); */
|
||||
fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n",
|
||||
// fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n",
|
||||
fprintf(fp, "/WORK/%s/%s /WORK/%s/%s[0]\n",
|
||||
chomped_circuit_name,
|
||||
original_output_name,
|
||||
original_output_name,
|
||||
my_strcat(chomped_circuit_name, formal_verification_top_postfix),
|
||||
my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix));
|
||||
my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix));
|
||||
}
|
||||
}
|
||||
}
|
||||
match_registers(fp, chomped_circuit_name);
|
||||
|
||||
for (h = 0; h < copy_nb_clusters; h++)
|
||||
clb_iteration(fp, chomped_circuit_name, h);
|
||||
|
||||
/* Run verification */
|
||||
fprintf(fp, "verify\n");
|
||||
fprintf(fp, "\n");
|
||||
/* Script END */
|
||||
fclose(fp);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue