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remove legacy codes of local encoders

This commit is contained in:
tangxifan 2019-09-10 15:34:20 -06:00
parent 5f561ef5e3
commit 82683d49cf
2 changed files with 1 additions and 233 deletions
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5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
View File

@ -156,10 +156,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
/* TODO: Generate modules into a .bak file now. Rename after it is verified */
std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name);
/* verilog_fname += ".bak"; */
/* Create the file stream */
std::fstream fp;
@ -208,7 +205,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
/* Close the file steam */
fp.close();
/* TODO: Add fname to the linked list when debugging is finished */
/* Add fname to the linked list when debugging is finished */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
}

229
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -2327,230 +2327,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,
return;
}
/***************************************************************************************
* Create a Verilog module for a encoder with a given output size
* Inputs
* | | | | |
* +-----------+
* / \
* / Encoder \
* +-----------------+
* | | | | | | | |
* Outputs
*
* The outputs are assumes to be one-hot codes (at most only one '1' exist)
* Considering this fact, there are only num_of_outputs conditions to be encoded.
* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
***************************************************************************************/
static
void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) {
/* Make sure we have a encoder which is at least 2 ! */
assert (2 <= num_outputs);
/* Get the number of inputs */
int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs);
/* Validate the FILE handler */
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d]Invalid file handler!\n",
__FILE__, __LINE__);
exit(1);
}
/* Print the name of encoder */
fprintf(fp, "//-------- Local Decoder convert %d-bit addr to %d-bit data \n",
num_inputs, num_outputs);
fprintf(fp, "module %s(", generate_verilog_decoder_subckt_name(num_inputs, num_outputs));
fprintf(fp, "\n");
/* Inputs */
dump_verilog_generic_port(fp, VERILOG_PORT_INPUT,
"addr",
0, num_inputs - 1);
fprintf(fp, ",\n");
/* Outputs */
fprintf(fp, "output ");
dump_verilog_generic_port(fp, VERILOG_PORT_REG,
"data",
0, num_outputs - 1);
fprintf(fp, ",\n");
dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT,
"data_inv",
0, num_outputs - 1);
fprintf(fp, "\n);\n");
/* Print the truth table of this encoder */
/* Internal logics */
/* We use a magic number -1 as the addr=1 should be mapped to ...1
* Otherwise addr will map addr=1 to ..10
* Note that there should be a range for the shift operators
* We should narrow the encoding to be applied to a given set of data
* This will lead to that any addr which falls out of the op code of data
* will give a all-zero code
* For example:
* data is 5-bit while addr is 3-bit
* data=8'b0_0000 will be encoded to addr=3'b001;
* data=8'b0_0001 will be encoded to addr=3'b010;
* data=8'b0_0010 will be encoded to addr=3'b011;
* data=8'b0_0100 will be encoded to addr=3'b100;
* data=8'b0_1000 will be encoded to addr=3'b101;
* data=8'b1_0000 will be encoded to addr=3'b110;
* The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
*/
fprintf(fp, "always@(addr)\n");
fprintf(fp, "case (addr)\n");
/* Create a string for addr and data */
for (int i = 0; i < num_outputs; ++i) {
fprintf(fp, "\t%d'b%s : data = %d'b%s;\n",
num_inputs, my_itobin(i, num_inputs),
num_outputs, my_ito1hot(i, num_outputs));
}
fprintf(fp, "\tdefault : data = %d'b%s;\n",
num_outputs, my_ito1hot(num_outputs - 1, num_outputs));
fprintf(fp, "endcase\n");
fprintf(fp, "assign data_inv = ~data;\n");
/* Finish */
fprintf(fp, "endmodule\n");
fprintf(fp, "//-------- END Local Decoder convert %d-bit addr to %d-bit data \n\n",
num_inputs, num_outputs);
return;
}
/* We should count how many multiplexers with different sizes are needed */
static
void dump_verilog_submodule_local_encoders(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* submodule_dir,
int num_switch,
t_switch_inf* switches,
t_spice* spice,
t_det_routing_arch* routing_arch,
bool is_explicit_mapping) {
/* Statisitcs for input sizes and structures of MUXes
* used in FPGA architecture
*/
/* We have linked list whichs stores spice model information of multiplexer*/
t_llist* muxes_head = NULL;
t_llist* temp = NULL;
FILE* fp = NULL;
char* verilog_name = my_strcat(submodule_dir, local_encoder_verilog_file_name);
int num_input_ports = 0;
t_spice_model_port** input_ports = NULL;
int num_sram_ports = 0;
t_spice_model_port** sram_ports = NULL;
int num_input_basis = 0;
t_spice_mux_model* cur_spice_mux_model = NULL;
/* Alloc the muxes*/
muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch);
/* Print the muxes netlist*/
fp = fopen(verilog_name, "w");
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name);
exit(1);
}
/* Generate the descriptions*/
dump_verilog_file_header(fp,"MUXes used in FPGA");
verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create a vector for local encoders with different sizes */
std::vector<int> encoder_sizes;
/* Make sure a clean start */
encoder_sizes.clear();
/* Print mux netlist one by one*/
temp = muxes_head;
while(temp) {
assert(NULL != temp->dptr);
cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr);
/* Bypass the spice models who has a user-defined subckt */
if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) {
input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE);
sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE);
assert(0 != num_input_ports);
assert(0 != num_sram_ports);
/* Check the Input port size */
if (cur_spice_mux_model->size != input_ports[0]->size) {
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n",
__FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size);
exit(1);
}
/* Check the SRAM port size */
num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size,
cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level);
if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level) != sram_ports[0]->size) {
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n",
__FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level*num_input_basis);
exit(1);
}
/* Move on to the next*/
temp = temp->next;
continue;
}
/* Bypass those without local encoders, we only care SPICE models whose type is MUX! */
if ( (SPICE_MODEL_MUX != cur_spice_mux_model->spice_model->type)
|| (FALSE == cur_spice_mux_model->spice_model->design_tech_info.mux_info->local_encoder) ) {
/* Move on to the next*/
temp = temp->next;
continue;
}
/* Reach here, we need to generate a local encoder Verilog module */
/* Generate the spice_mux_arch */
cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch));
init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size);
/* We will bypass all the TREE-LIKE multiplexers and those with 2-inputs */
if ( (SPICE_MODEL_STRUCTURE_TREE == cur_spice_mux_model->spice_mux_arch->structure)
|| ( 2 == cur_spice_mux_model->spice_mux_arch->num_input) ) {
/* Move on to the next*/
temp = temp->next;
continue;
}
/* Find the size of local encoders */
std::vector<int>::iterator it = std::find(encoder_sizes.begin(), encoder_sizes.end(), cur_spice_mux_model->spice_mux_arch->num_input_basis);
/* See if a same-sized local encoder is already in the list */
if (it == encoder_sizes.end()) {
/* Need to add to the list */
encoder_sizes.push_back(cur_spice_mux_model->spice_mux_arch->num_input_basis);
}
/* Move on to the next*/
temp = temp->next;
}
/* Print the local encoder subckt */
for (size_t i = 0; i < encoder_sizes.size(); ++i) {
dump_verilog_mux_local_encoder_module(fp, encoder_sizes[i]);
}
vpr_printf(TIO_MESSAGE_INFO,"Generated %d local encoders for Multiplexers.\n",
encoder_sizes.size());
/* Add fname to the linked list */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
/* Close the file*/
fclose(fp);
/* remember to free the linked list*/
free_muxes_llist(muxes_head);
/* Free strings */
free(verilog_name);
return;
}
static
void dump_verilog_wire_module(FILE* fp,
char* wire_subckt_name,
@ -3559,11 +3335,6 @@ void dump_verilog_submodules(ModuleManager& module_manager,
verilog_dir, submodule_dir);
vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n");
/*
dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch,
switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
*/
print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
/* 2. LUTes */