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refactoring module manager

This commit is contained in:
tangxifan 2019-08-23 12:52:01 -06:00
parent 520630c5e2
commit 931b042750
4 changed files with 67 additions and 39 deletions
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37
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
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@ -15,43 +15,6 @@
/******************************************************************************
* Public Mutators
******************************************************************************/
/* Add a module based on its circuit-level description */
ModuleId ModuleManager::add_module_with_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
ModuleId module = add_module(circuit_lib.model_name(circuit_model));
/* Add ports */
/* Find global ports and add one by one */
for (const auto& port : circuit_lib.model_global_ports(circuit_model)) {
BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
add_port(module, port_info, MODULE_GLOBAL_PORT);
}
/* Find other ports and add one by one */
/* Create a type-to-type map for ports */
std::map<enum e_spice_model_port_type, enum e_module_port_type> port_type2type_map;
port_type2type_map[SPICE_MODEL_PORT_INOUT] = MODULE_INOUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_INPUT] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_CLOCK] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_SRAM] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_BL] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_BLB] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_WL] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_WLB] = MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = MODULE_OUTPUT_PORT;
/* Input ports (ignore all the global ports when searching the circuit_lib */
for (const auto& kv : port_type2type_map) {
for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) {
BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
add_port(module, port_info, kv.second);
}
}
/* Return the new id */
return module;
}
/* Add a module */
ModuleId ModuleManager::add_module(const std::string& name) {
/* Find if the name has been used. If used, return an invalid Id and report error! */

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
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@ -22,7 +22,7 @@
#include "device_port.h"
class ModuleManager {
private: /* Private data structures */
public: /* Private data structures */
enum e_module_port_type {
MODULE_GLOBAL_PORT,
MODULE_INOUT_PORT,
@ -34,7 +34,6 @@ class ModuleManager {
public: /* Public Constructors */
public: /* Public mutators */
/* Add a module */
ModuleId add_module_with_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model);
ModuleId add_module(const std::string& name);
/* Add a port to a module */
ModulePortId add_port(const ModuleId& module,

52
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp Normal file
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@ -0,0 +1,52 @@
/******************************************************************************
* This files includes most utilized functions
* for data structures for module management.
******************************************************************************/
#include <map>
#include <algorithm>
#include "vtr_assert.h"
#include "spice_types.h"
#include "circuit_library.h"
#include "module_manager.h"
#include "module_manager_utils.h"
ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) {
ModuleId module = module_manager.add_module(circuit_lib.model_name(circuit_model));
/* Add ports */
/* Find global ports and add one by one */
for (const auto& port : circuit_lib.model_global_ports(circuit_model)) {
BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);
}
/* Find other ports and add one by one */
/* Create a type-to-type map for ports */
std::map<enum e_spice_model_port_type, ModuleManager::e_module_port_type> port_type2type_map;
port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT;
port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT;
/* Input ports (ignore all the global ports when searching the circuit_lib */
for (const auto& kv : port_type2type_map) {
for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) {
BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
module_manager.add_port(module, port_info, kv.second);
}
}
/* Return the new id */
return module;
}

14
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h Normal file
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@ -0,0 +1,14 @@
/******************************************************************************
* This files includes declarations for most utilized functions
* for data structures for module management.
******************************************************************************/
#ifndef MODULE_MANAGER_UTILS_H
#define MODULE_MANAGER_UTILS_H
ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model);
#endif