From 931b042750855e79e9fedede516db3f3306aec07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 12:52:01 -0600 Subject: [PATCH] refactoring module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 37 ------------- .../vpr/SRC/fpga_x2p/base/module_manager.h | 3 +- .../fpga_x2p/base/module_manager_utils.cpp | 52 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 14 +++++ 4 files changed, 67 insertions(+), 39 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index a260ab626..2affed6a4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -15,43 +15,6 @@ /****************************************************************************** * Public Mutators ******************************************************************************/ -/* Add a module based on its circuit-level description */ -ModuleId ModuleManager::add_module_with_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - ModuleId module = add_module(circuit_lib.model_name(circuit_model)); - - /* Add ports */ - /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - add_port(module, port_info, MODULE_GLOBAL_PORT); - } - - /* Find other ports and add one by one */ - /* Create a type-to-type map for ports */ - std::map port_type2type_map; - port_type2type_map[SPICE_MODEL_PORT_INOUT] = MODULE_INOUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_INPUT] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_CLOCK] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_SRAM] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BL] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BLB] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WL] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WLB] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = MODULE_OUTPUT_PORT; - - /* Input ports (ignore all the global ports when searching the circuit_lib */ - for (const auto& kv : port_type2type_map) { - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - add_port(module, port_info, kv.second); - } - } - - /* Return the new id */ - return module; -} - /* Add a module */ ModuleId ModuleManager::add_module(const std::string& name) { /* Find if the name has been used. If used, return an invalid Id and report error! */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index fc3d14ab3..553974a7c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -22,7 +22,7 @@ #include "device_port.h" class ModuleManager { - private: /* Private data structures */ + public: /* Private data structures */ enum e_module_port_type { MODULE_GLOBAL_PORT, MODULE_INOUT_PORT, @@ -34,7 +34,6 @@ class ModuleManager { public: /* Public Constructors */ public: /* Public mutators */ /* Add a module */ - ModuleId add_module_with_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); ModuleId add_module(const std::string& name); /* Add a port to a module */ ModulePortId add_port(const ModuleId& module, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp new file mode 100644 index 000000000..f375c446c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -0,0 +1,52 @@ +/****************************************************************************** + * This files includes most utilized functions + * for data structures for module management. + ******************************************************************************/ + +#include +#include + +#include "vtr_assert.h" + +#include "spice_types.h" + +#include "circuit_library.h" +#include "module_manager.h" +#include "module_manager_utils.h" + +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { + ModuleId module = module_manager.add_module(circuit_lib.model_name(circuit_model)); + + /* Add ports */ + /* Find global ports and add one by one */ + for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); + } + + /* Find other ports and add one by one */ + /* Create a type-to-type map for ports */ + std::map port_type2type_map; + port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT; + + /* Input ports (ignore all the global ports when searching the circuit_lib */ + for (const auto& kv : port_type2type_map) { + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module, port_info, kv.second); + } + } + + /* Return the new id */ + return module; + +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h new file mode 100644 index 000000000..6868b71f7 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -0,0 +1,14 @@ +/****************************************************************************** + * This files includes declarations for most utilized functions + * for data structures for module management. + ******************************************************************************/ + +#ifndef MODULE_MANAGER_UTILS_H +#define MODULE_MANAGER_UTILS_H + +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); + + +#endif +