add missing files and try to refactor submodule essential

2019-08-20 16:12:01 -06:00 · 2019-08-20 16:12:01 -06:00 · 59f1ac7310
parent 5f55fc7b49
commit 59f1ac7310
2 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/tasks/basic_flow/latest
+++ b/openfpga_flow/tasks/basic_flow/latest
@ -1 +0,0 @@
-run003
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp
@ -263,6 +263,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir,
                                        const CircuitLibrary& circuit_lib) {
  /* TODO: remove .bak when this part is completed and tested */
  std::string verilog_fname = submodule_dir + essentials_verilog_file_name + ".bak";
+
  std::fstream fp;

  /* Create the file stream */