tangxifan
|
85644d07ae
|
refactoring pb interc Verilog generation
|
2019-10-12 21:55:53 -06:00 |
|
tangxifan
|
d1948c82eb
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
tangxifan
|
b3ca0d32a4
|
remove configuration bus naming dependency on SRAM circuit models
|
2019-10-11 19:47:36 -06:00 |
|
tangxifan
|
73a5977e0d
|
Debugged Verilog generation for primitive pb_types
|
2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
|
bug fixing in Verilog port merging and instanciation
|
2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
|
2019-10-11 13:07:14 -06:00 |
|
tangxifan
|
c9950162d1
|
start plug in new Verilog writer. Start debugging
|
2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
|
tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
|
2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
|
start implementing module graph-based connection
|
2019-10-09 20:30:16 -06:00 |
|
tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
|
2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
|
2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
6bed89c237
|
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
|
2019-10-08 18:00:04 -06:00 |
|
tangxifan
|
ea2942640e
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
|
add module name generation for pb_types
|
2019-10-07 21:09:54 -06:00 |
|
tangxifan
|
86c9af872e
|
refactoring physical block Verilog generation
|
2019-10-07 17:39:00 -06:00 |
|
tangxifan
|
997bfdbb95
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
tangxifan
|
3ca6f08aa4
|
start refactoring physical block Verilog generation
|
2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
tangxifan
|
393f0b0ac3
|
align formal verification port inside refactored routing blocks
|
2019-10-05 21:16:48 -06:00 |
|
tangxifan
|
86387ff79c
|
Merge branch 'refactoring' into dev
|
2019-10-05 18:15:31 -06:00 |
|
tangxifan
|
c920047ee8
|
refactored Verilog generation for connection blocks
|
2019-10-05 18:14:23 -06:00 |
|
tangxifan
|
2d7e8d9811
|
add check codes for memory buses
|
2019-10-05 11:07:26 -06:00 |
|
tangxifan
|
6b301d9f44
|
Merge branch 'dev' into refactoring
|
2019-10-04 22:47:29 -06:00 |
|
tangxifan
|
b905c0c68c
|
refactored memory module Verilog generation for scan-chains
|
2019-10-04 22:45:45 -06:00 |
AurelienUoU
|
7aa24f407e
|
Fix explicit port name in CBs
|
2019-10-04 11:20:46 -06:00 |
Baudouin Chauviere
|
6f7023658e
|
Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
|
2019-10-03 14:59:04 -06:00 |
|
Baudouin Chauviere
|
95596bb4f8
|
Correction on the cb vs sb corrdinator. Does not fix the problem though
|
2019-10-03 13:50:01 -06:00 |
|
Baudouin Chauviere
|
01ff484158
|
Explicit verilog passing all tests
|
2019-10-02 10:22:28 -06:00 |
|
Baudouin Chauviere
|
6b3e1fd410
|
Get backup verilog_routing.c
|
2019-10-02 08:54:56 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
|
2019-10-01 16:40:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
|
2019-10-01 14:49:42 -06:00 |
|
tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
|
2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
|
2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
|
make local configuration bus generation more general
|
2019-09-28 21:02:14 -06:00 |
Ganesh Gore
|
069f628bb0
|
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
|
2019-09-28 11:21:37 -06:00 |
|
tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
|
2019-09-27 23:10:43 -06:00 |
|
tangxifan
|
4da5035627
|
Connect CCFFs in a chain in a Verilog module
|
2019-09-27 20:50:12 -06:00 |
|
tangxifan
|
f0949fea2f
|
Merge branch 'dev' into refactoring
|
2019-09-27 18:09:58 -06:00 |
|
tangxifan
|
1e187f3d15
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
AurelienUoU
|
640922accd
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-27 16:54:13 -06:00 |
|
AurelienUoU
|
a93d7e57f7
|
Scan chain support in directlist
|
2019-09-27 16:53:00 -06:00 |
|
tangxifan
|
167778cf57
|
refactoring MUX Verilog instanciation in Switch block
|
2019-09-27 16:05:47 -06:00 |
|
Ganesh Gore
|
438b592a8a
|
Appended VPR to genereate INI File
|
2019-09-27 14:00:27 -06:00 |
|
Ganesh Gore
|
a3e9b4aea9
|
Added mINI/lib - INI Read write to project
|
2019-09-27 13:58:48 -06:00 |
|
tangxifan
|
dbe1625267
|
Refactored Verilog wiring for formal verification ports in Switch Blocks
|
2019-09-27 13:51:22 -06:00 |
|
tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
091bbd4d9c
|
start refactoring the num_config_bits for circuit model
|
2019-09-26 22:53:07 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |
|
tangxifan
|
f0589cc2cf
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
|
tangxifan
|
05eaa412b1
|
refactored short-connection of switch block
|
2019-09-26 14:31:05 -06:00 |
|
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
tangxifan
|
ea0da49e04
|
Merge branch 'dev' into refactoring
|
2019-09-25 21:06:06 -06:00 |
|
tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
|
2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
|
2019-09-23 20:25:53 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
|
2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
1e4177067d
|
remove port size in the module definition
|
2019-09-22 11:21:43 -06:00 |
|
tangxifan
|
0ff0c8cf06
|
bug fix for IO=1
|
2019-09-19 15:43:25 -06:00 |
|
tangxifan
|
e0b253d30a
|
minor fix for non-LUT intermedate buffer case
|
2019-09-18 15:15:03 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
2294aecef2
|
remove old codes and compact new codes
|
2019-09-16 20:19:14 -06:00 |
|
tangxifan
|
c5ee81541a
|
remove dead codes in routing module generation
|
2019-09-16 18:47:01 -06:00 |
|
tangxifan
|
0963852091
|
remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
|
2019-09-16 18:38:37 -06:00 |
|
tangxifan
|
d83cad7c2e
|
refactoring Verilog generation for routing channels
|
2019-09-16 17:35:51 -06:00 |
|
Baudouin Chauviere
|
d5ebe66ad9
|
Bug fix
|
2019-09-16 10:57:52 -06:00 |
|
Ganesh Gore
|
d90329678a
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-09-14 12:11:36 -06:00 |
|
Ganesh Gore
|
ec3854a648
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-14 00:14:17 -06:00 |
|
tangxifan
|
f69ce708ca
|
rework on the order of top-level functions
|
2019-09-13 21:59:52 -06:00 |
|
tangxifan
|
29e80d157c
|
Start developing BitstreamContext
|
2019-09-13 21:27:47 -06:00 |
|
tangxifan
|
e64cfc5852
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
Baudouin Chauviere
|
737cfb1086
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-09-13 16:02:06 -06:00 |
|
Baudouin Chauviere
|
63e6ed21b5
|
Fully functional
|
2019-09-13 16:02:06 -06:00 |
|
tangxifan
|
d6fc9c1c71
|
Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
|
2019-09-13 15:36:35 -06:00 |
|
tangxifan
|
009c0d63b5
|
refactored the memory bank. Ready to plug-in the test
|
2019-09-13 15:05:31 -06:00 |
|
tangxifan
|
99c30fa7dd
|
keep refactoring the memory Verilog generation
|
2019-09-13 14:02:04 -06:00 |
|
tangxifan
|
56f40cf46c
|
light modification on Verilog Mux generation and start refactoring memory Verilog generation
|
2019-09-13 12:22:57 -06:00 |
|
tangxifan
|
d8b9349066
|
remove legacy codes
|
2019-09-13 11:48:25 -06:00 |
|
tangxifan
|
b920f0fc38
|
refactored user template Verilog generation
|
2019-09-13 11:41:54 -06:00 |
|
tangxifan
|
0e6c88dd52
|
delete legacy codes for wire Verilog generation
|
2019-09-12 21:06:53 -06:00 |
|
tangxifan
|
c20e182484
|
plugged in the refactored wire Verilog generation
|
2019-09-12 20:56:30 -06:00 |
|
tangxifan
|
2b829238b5
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
tangxifan
|
79fa858f36
|
remove unused ports for Verilog modules
|
2019-09-11 19:39:59 -06:00 |
|
tangxifan
|
2bed51bf29
|
minor bug fix for echo
|
2019-09-11 17:41:45 -06:00 |
|
tangxifan
|
0399319212
|
refactored LUT Verilog generation
|
2019-09-11 17:04:43 -06:00 |
|
tangxifan
|
6a5b50facf
|
refactored RRAM MUX verilog generation
|
2019-09-10 20:45:44 -06:00 |
|
tangxifan
|
0711aa1bd6
|
minor bug fixing
|
2019-09-10 16:56:14 -06:00 |
|
tangxifan
|
82683d49cf
|
remove legacy codes of local encoders
|
2019-09-10 15:34:20 -06:00 |
|
tangxifan
|
5f561ef5e3
|
pass regression test when plug in refactored local encoders
|
2019-09-10 15:26:47 -06:00 |
|
tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
|
2019-09-10 15:16:29 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
tangxifan
|
59edd49862
|
refactored CMOS MUX buffering
|
2019-09-06 16:39:34 -06:00 |
|
tangxifan
|
bc9d95408e
|
bug fixed and refactored intermediate buffer addition
|
2019-09-05 16:09:28 -06:00 |
|
tangxifan
|
e623c19055
|
implementing mux Verilog generation. Bugs detected, fixing ongoing
|
2019-09-04 23:54:53 -06:00 |
|
tangxifan
|
fde9c8b4ec
|
add frac_lut outputs to mux_graph generation
|
2019-09-03 23:19:24 -06:00 |
|
tangxifan
|
b6bb433edc
|
bug fixing for datapath mux size in Verilog generation
|
2019-09-03 18:09:21 -06:00 |
|
tangxifan
|
4d183a3fe4
|
start developing mux Verilog module generation
|
2019-09-03 16:59:03 -06:00 |
|
tangxifan
|
a8c803f08f
|
try to fix bugs in explicit port mapping
|
2019-09-02 16:37:43 -06:00 |
|
tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
|
2019-09-02 16:21:29 -06:00 |
|
tangxifan
|
395bf4fbdf
|
refactored rram mux generation
|
2019-09-02 14:30:18 -06:00 |
|
tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
|
2019-08-27 18:39:25 -06:00 |
|
tangxifan
|
ab6f1a5461
|
add mux output ids for mux_graph
|
2019-08-26 21:21:50 -06:00 |
|
tangxifan
|
b6617a5adf
|
fix bugs in verilog comment lines
|
2019-08-25 16:37:46 -06:00 |
|
tangxifan
|
14db2bf1a9
|
minor fixing on comment
|
2019-08-25 16:35:49 -06:00 |
|
tangxifan
|
706b7f3427
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-25 15:52:04 -06:00 |
|
tangxifan
|
1cfc117b32
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 15:47:57 -06:00 |
|
tangxifan
|
056c45321b
|
plug in module manager
|
2019-08-25 15:44:31 -06:00 |
|
tangxifan
|
8fc258cc93
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-25 15:33:37 -06:00 |
|
tangxifan
|
c43fabb43c
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 10:31:45 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
|
2019-08-23 16:36:30 -06:00 |
|
tangxifan
|
931b042750
|
refactoring module manager
|
2019-08-23 12:52:01 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
|
2019-08-22 23:49:35 -06:00 |
|
tangxifan
|
3f45e6cc87
|
remove dead codes for essential gates code generation
|
2019-08-22 10:01:52 -06:00 |
|
tangxifan
|
43de2d7636
|
some tuning on Verilog port formatting
|
2019-08-21 23:47:50 -06:00 |
|
tangxifan
|
1be5632e92
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
tangxifan
|
7b0c55ce15
|
try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
|
2019-08-21 22:45:48 -06:00 |
|
tangxifan
|
5a40c6713d
|
managed to plug in refactored essential gates, dead codes to be removed
|
2019-08-21 21:50:26 -06:00 |
|
tangxifan
|
d8eb9866a0
|
refactored gate verilog generation
|
2019-08-21 18:49:48 -06:00 |
|
tangxifan
|
b08ff465c9
|
refactored pass-gate verilog generation
|
2019-08-21 17:33:16 -06:00 |
|
tangxifan
|
5e156dc725
|
minor fix for OSX and update travis using ccache to speed up compilation
|
2019-08-21 15:25:36 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
|
2019-08-20 21:56:55 -06:00 |
|
tangxifan
|
19472ace4e
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
bee070d7cc
|
start plug in MUX library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
893683fa95
|
start developing mux library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
153d506abb
|
add graph-based mux decoding function
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
dcca9f4f0f
|
finish mux graph builders
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
638969c3c9
|
adding mux graph data structures
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
0b8473e960
|
start developing graphs for muxes, with aims to simplify netlist and bitstream generation
|
2019-08-20 15:24:52 -06:00 |
|
Ganesh Gore
|
69ffc38645
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-19 21:59:06 -06:00 |
|
Ganesh Gore
|
7bfc48b8e4
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
|
tangxifan
|
e456b6f905
|
replace spice_models with circuit model in bitstream generator
|
2019-08-16 16:36:49 -06:00 |
|
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
|
tangxifan
|
b66e120366
|
patch on local encoders for unused configuration, avoid chip-burn issues
|
2019-08-16 15:32:23 -06:00 |
|
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
|
AurelienUoU
|
8e38aa6019
|
Merge with heterogeneous for unfracturable LUT bug fix
|
2019-08-14 10:10:27 -06:00 |
|
AurelienUoU
|
df873903f8
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
|
AurelienUoU
|
30c0f2b6b7
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-14 09:11:54 -06:00 |
|
AurelienUoU
|
90aaed6e1f
|
Fix regression test
|
2019-08-14 09:10:13 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
|
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
|
2019-08-13 15:37:42 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
AurelienUoU
|
8dab4dec90
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-13 11:09:29 -06:00 |
|
AurelienUoU
|
7851246424
|
Resolve merge issue
|
2019-08-13 11:08:30 -06:00 |
|
AurelienUoU
|
2da4d3f33c
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-12 09:57:02 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
|
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
AurelienUoU
|
40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-29 11:45:23 -06:00 |
|
tangxifan
|
32e3a556b9
|
bug fixing herited from explicit mapping
|
2019-07-17 09:26:05 -06:00 |
|
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
|
2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
|
2019-07-17 08:36:09 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
|
2019-07-17 07:54:23 -06:00 |
|
tangxifan
|
e9154b1f74
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 14:42:45 -06:00 |
|
tangxifan
|
115411941b
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 13:15:45 -06:00 |
|
Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
Baudouin Chauviere
|
e602006a07
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-16 12:45:13 -06:00 |
|
AurelienUoU
|
b810b5cab9
|
fpga_flow bug fix + upload k8 architecture
|
2019-07-16 07:04:45 -06:00 |
|
AurelienUoU
|
35e1962732
|
Merge branch 'dev' into documentation
|
2019-07-15 21:19:26 -06:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |