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bug fixing in Verilog port merging and instanciation

This commit is contained in:
tangxifan 2019-10-11 14:20:04 -06:00
parent 663b1b7665
commit 50f7d1eae3
4 changed files with 24 additions and 13 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
View File

@ -50,7 +50,7 @@ std::vector<size_t> ModuleManager::child_module_instances(const ModuleId& parent
VTR_ASSERT(child_index != children_[parent_module].size());
/* Create a vector, with sequentially increasing numbers */
std::vector<size_t> instance_range(num_child_instances_[parent_module][child_index]);
std::vector<size_t> instance_range(num_child_instances_[parent_module][child_index], 0);
std::iota(instance_range.begin(), instance_range.end(), 0);
return instance_range;

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
View File

@ -474,6 +474,9 @@ void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_m
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) {
ModuleNetId net = module_manager.create_module_net(parent_module);
/* TODO: Give a name to make it clear */
std::string net_name = module_manager.module_name(logic_module) + std::string("_") + logic_module_sram_ports[port_index].get_name();
module_manager.set_net_name(parent_module, net, net_name);
/* Add net source */
module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]);
/* Add net sink */

14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
View File

@ -50,6 +50,7 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag
}
/* Reach here, this is a local wire */
std::string net_name;
/* Each net must only one 1 source */
@ -64,9 +65,14 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag
/* Get the pin id */
size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)];
net_name = module_manager.module_name(net_src_module);
net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
net_name += module_manager.module_port(module_id, net_src_port).get_name();
/* Load user-defined name if we have it */
if (false == module_manager.net_name(module_id, module_net).empty()) {
net_name = module_manager.net_name(module_id, module_net);
} else {
net_name = module_manager.module_name(net_src_module);
net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
net_name += module_manager.module_port(module_id, net_src_port).get_name();
}
return BasicPort(net_name, net_src_pin, net_src_pin);
}
@ -213,7 +219,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
/* Print module name */
fp << "\t" << module_manager.module_name(child_module) << " ";
/* Print instance name, <name>_<num_instance_in_parent_module> */
fp << module_manager.module_name(child_module) << "_" << module_manager.num_instance(parent_module, child_module) << "_" << " (" << std::endl;
fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
/* Print each port with/without explicit port map */
/* port type2type mapping */

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -464,19 +464,16 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
continue;
}
/* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
bool merged = false;
for (auto& merged_port : merged_ports) {
if (0 != port.get_name().compare(merged_port.get_name())) {
/* Unable to merge, add the port to merged port list */
merged_ports.push_back(port);
/* Go to next */
break;
/* Unable to merge, Go to next */
continue;
}
/* May be merged, check LSB of port and MSB of merged_port */
if (merged_port.get_msb() + 1 != port.get_lsb()) {
/* Unable to merge, add the port to merged port list */
merged_ports.push_back(port);
/* Go to next */
break;
/* Unable to merge, Go to next */
continue;
}
/* Reach here, we should merge the ports,
* LSB of merged_port remains the same,
@ -484,8 +481,13 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
* to the MSB of port
*/
merged_port.set_msb(port.get_msb());
merged = true;
break;
}
if (false == merged) {
/* Unable to merge, add the port to merged port list */
merged_ports.push_back(port);
}
}
return merged_ports;