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Correction on the cb vs sb corrdinator. Does not fix the problem though

This commit is contained in:
Baudouin Chauviere 2019-10-03 13:50:01 -06:00
parent db059af8b8
commit 95596bb4f8
1 changed files with 4 additions and 4 deletions
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8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
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@ -953,13 +953,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
/* Print each INPUT Pins of a grid */
if (true == is_explicit_mapping) {
if (RIGHT == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type) + 1, unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (TOP == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (LEFT == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
} else if (BOTTOM == side_manager.get_side()) {
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num);
}
}
dump_verilog_grid_side_pin_with_given_index(fp, OPIN,