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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)

This commit is contained in:
tangxifan 2019-08-21 22:45:48 -06:00
parent 5a40c6713d
commit 7b0c55ce15
2 changed files with 12 additions and 18 deletions
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20
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
View File

@ -68,11 +68,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
/* MUX graph must have only 1 level*/
VTR_ASSERT(1 == mux_graph.num_levels());
/* Comment lines */
fp << "//---- Structural Verilog for CMOS MUX basis module:" << module_name << "-----" << std::endl;
/* Print the port list and definition */
fp << "module " << module_name << "(" << std::endl;
/* Print Verilog module */
print_verilog_module_definition(fp, module_name);
/* Create port information */
/* Configure each input port */
@ -103,7 +100,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
fp << ");" << std::endl;
/* Verilog Behavior description for a MUX */
fp << "//---- Structure-level description -----" << std::endl;
print_verilog_comment(fp, std::string("---- Structure-level description -----"));
/* Special case: only one memory, switch case is simpler
* When mem = 1, propagate input 0;
* when mem = 0, propagate input 1;
@ -172,13 +169,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
}
}
/* Put an end to this module */
fp << "endmodule" << std::endl;
/* Comment lines */
fp << "//---- END Structural Verilog CMOS MUX basis module: " << module_name << "-----" << std::endl << std::endl;
return;
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
}
/***********************************************
@ -224,7 +216,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp,
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n",
__FILE__, __LINE__, circuit_lib.model_name(circuit_model));
__FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str());
exit(1);
}

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
View File

@ -21,10 +21,12 @@
#include "verilog_submodule_utils.h"
/* All values are printed with this precision value. The higher the
* value, the more accurate timing assignment is. Using numeric_limits
* max_digits10 guarentees that no values change during a sequence of
* float -> string -> float conversions */
constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10;
* value, the more accurate timing assignment is. Using a number of 6
* guarentees that a precision of femtosecond which is sufficent for
* electrical simulation (simulation timescale is 10-9
*/
/* constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10; */
constexpr int FLOAT_PRECISION = 6;
/************************************************
* Print a timing matrix defined in theecircuit model