diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
index 2d12c11d7..9255097c9 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
@@ -68,11 +68,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
   /* MUX graph must have only 1 level*/
   VTR_ASSERT(1 == mux_graph.num_levels());
 
-  /* Comment lines */
-  fp << "//---- Structural Verilog for CMOS MUX basis module:" << module_name << "-----" << std::endl;
-
-  /* Print the port list and definition */
-  fp << "module " << module_name << "(" << std::endl;
+  /* Print Verilog module */
+  print_verilog_module_definition(fp, module_name);
 
   /* Create port information */
   /* Configure each input port */
@@ -103,7 +100,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
   fp << ");" << std::endl;
 
   /* Verilog Behavior description for a MUX */
-  fp << "//---- Structure-level description -----" << std::endl;
+  print_verilog_comment(fp, std::string("---- Structure-level description -----"));
   /* Special case: only one memory, switch case is simpler 
    * When mem = 1, propagate input 0; 
    * when mem = 0, propagate input 1;
@@ -172,13 +169,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
     }
   }
 
-  /* Put an end to this module */
-  fp << "endmodule" << std::endl;
-
-  /* Comment lines */
-  fp << "//---- END Structural Verilog CMOS MUX basis module: " << module_name << "-----" << std::endl << std::endl;
-
-  return;
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
 }
 
 /***********************************************
@@ -224,7 +216,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp,
   default:
     vpr_printf(TIO_MESSAGE_ERROR,
                "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n",
-               __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); 
+               __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); 
     exit(1);
   }
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
index af28fc494..191e1f7d3 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
@@ -21,10 +21,12 @@
 #include "verilog_submodule_utils.h"
 
 /* All values are printed with this precision value. The higher the
- * value, the more accurate timing assignment is. Using numeric_limits
- * max_digits10 guarentees that no values change during a sequence of
- * float -> string -> float conversions */
-constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10;
+ * value, the more accurate timing assignment is. Using a number of 6
+ * guarentees that a precision of femtosecond which is sufficent for 
+ * electrical simulation (simulation timescale is 10-9 
+ */
+/* constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10; */
+constexpr int FLOAT_PRECISION = 6; 
 
 /************************************************
  * Print a timing matrix defined in theecircuit model