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remove unused ports for Verilog modules

This commit is contained in:
tangxifan 2019-09-11 19:39:59 -06:00
parent 2bed51bf29
commit 79fa858f36
5 changed files with 47 additions and 11 deletions
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34
vpr7_x2p/libarchfpga/SRC/circuit_library.cpp
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@ -529,7 +529,8 @@ std::vector<CircuitPortId> CircuitLibrary::model_global_ports(const CircuitModel
/* Recursively find all the global ports in the circuit model / sub circuit_model */
std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type,
const bool& recursive) const {
const bool& recursive,
const std::vector<enum e_spice_model_type>& ignore_model_types) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
@ -556,7 +557,21 @@ std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const Circ
/* If go recursively, we search all the buffer/pass-gate circuit model ids */
/* Go search every sub circuit model included the current circuit model */
for (const auto& sub_model : sub_models_[model_id]) {
std::vector<CircuitPortId> sub_global_ports = model_global_ports_by_type(sub_model, type, recursive);
/* Bypass this sub model if user specified an ignore list */
bool ignore = false;
for (const auto& ignore_model_type : ignore_model_types) {
if (ignore_model_type != model_type(sub_model)) {
continue;
}
ignore = true;
break;
}
if (true == ignore) {
continue;
}
/* Now we can add global ports */
std::vector<CircuitPortId> sub_global_ports = model_global_ports_by_type(sub_model, type, recursive, ignore_model_types);
for (const auto& sub_global_port : sub_global_ports) {
/* Add to global_ports, if it is not already found in the list */
bool add_to_list = true;
@ -577,6 +592,21 @@ std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const Circ
return global_ports;
}
/* Recursively find all the global ports in the circuit model / sub circuit_model
* but ignore all the SRAM and SCFF, which are configuration memories
*/
std::vector<CircuitPortId> CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type,
const bool& recursive,
const bool& ignore_config_memories) const {
std::vector<enum e_spice_model_type> ignore_list;
if (true == ignore_config_memories) {
ignore_list.push_back(SPICE_MODEL_SRAM);
ignore_list.push_back(SPICE_MODEL_SCFF);
}
return model_global_ports_by_type(model_id, type, recursive, ignore_list);
}
/* Find the ports of a circuit model by a given type, return a list of qualified ports */
std::vector<CircuitPortId> CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type) const {

8
vpr7_x2p/libarchfpga/SRC/circuit_library.h
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@ -256,7 +256,13 @@ class CircuitLibrary {
std::vector<CircuitPortId> model_global_ports(const CircuitModelId& model_id, const bool& recursive) const;
std::vector<CircuitPortId> model_global_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type,
const bool& recursive) const;
const bool& recursive,
const std::vector<enum e_spice_model_type>& ignore_model_types) const;
std::vector<CircuitPortId> model_global_ports_by_type(const CircuitModelId& model_id,
const enum e_spice_model_port_type& type,
const bool& recursive,
const bool& ignore_config_memories) const;
std::vector<CircuitPortId> model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const;
std::vector<CircuitPortId> model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const;
std::vector<CircuitPortId> model_input_ports(const CircuitModelId& model_id) const;

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp
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@ -148,7 +148,7 @@ void print_verilog_invbuf_module(ModuleManager& module_manager,
/* Find the input port, output port and global inputs*/
std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Make sure:
* There is only 1 input port and 1 output port,
@ -233,7 +233,7 @@ void print_verilog_passgate_module(ModuleManager& module_manager,
/* Find the input port, output port*/
std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
case SPICE_MODEL_PASS_GATE_TRANSMISSION:
@ -444,7 +444,7 @@ void print_verilog_gate_module(ModuleManager& module_manager,
/* Find the input port, output port*/
std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Make sure:
* There is only 1 output port,

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp
View File

@ -45,7 +45,7 @@ void print_verilog_submodule_lut(ModuleManager& module_manager,
check_file_handler(fp);
/* Get the global ports required by MUX (and any submodules) */
std::vector<CircuitPortId> lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Get the input ports from the mux */
std::vector<CircuitPortId> lut_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
/* Get the output ports from the mux */

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
View File

@ -200,7 +200,7 @@ void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager,
return;
}
std::vector<CircuitPortId> tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Make sure we have a valid file handler*/
check_file_handler(fp);
@ -641,7 +641,7 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager,
/* Add module ports */
/* Add each global programming enable/disable ports */
std::vector<CircuitPortId> prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
for (const auto& port : prog_enable_ports) {
/* Configure each global port */
BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
@ -1310,7 +1310,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager,
const std::string& module_name,
const MuxGraph& mux_graph) {
/* Get the global ports required by MUX (and any submodules) */
std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Get the input ports from the mux */
std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
/* Get the output ports from the mux */
@ -1726,7 +1726,7 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager,
}
/* Get the global ports required by MUX (and any submodules) */
std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true);
/* Get the input ports from the mux */
std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
/* Get the output ports from the mux */