Debugged Verilog generation for primitive pb_types
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tangxifan
parent
50f7d1eae3
commit
73a5977e0d
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@ -583,11 +583,209 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
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}
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}
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/********************************************************************
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/*********************************************************************
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* Add the port-to-port connection between all the memory modules
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* and their parent module
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*
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* Create nets to wire the control signals of memory module to
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* the configuration ports of primitive module
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*
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* Configuration Chain
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* -------------------
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*
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* config_bus (head) config_bus (tail)
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* | ^
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* primitive | |
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* +---------------------------------------------+
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* | | | |
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* | v | |
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* | +-------------------------------------+ |
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* | | CMOS-based Memory Modules | |
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* | +-------------------------------------+ |
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* | | | |
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* | v v |
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* | sram_out sram_outb |
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* | |
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* +---------------------------------------------+
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*
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* Memory bank
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* -----------
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*
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* config_bus (BL) config_bus (WL)
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* | |
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* primitive | |
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* +---------------------------------------------+
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* | | | |
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* | v v |
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* | +-------------------------------------+ |
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* | | CMOS-based Memory Modules | |
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* | +-------------------------------------+ |
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* | | | |
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* | v v |
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* | sram_out sram_outb |
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* | |
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* +---------------------------------------------+
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*
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**********************************************************************/
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static
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void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::vector<ModuleId>& memory_modules,
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const std::vector<size_t>& memory_instances,
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const e_sram_orgz& sram_orgz_type,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitModelId>& memory_models) {
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/* Ensure that the size of memory_model vector matches the memory_module vector */
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VTR_ASSERT( (memory_modules.size() == memory_instances.size())
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&& (memory_modules.size() == memory_models.size()) );
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switch (sram_orgz_type) {
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case SPICE_SRAM_STANDALONE:
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/* Nothing to do */
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break;
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case SPICE_SRAM_SCAN_CHAIN: {
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/* Connect all the memory modules under the parent module in a chain
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*
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* +--------+ +--------+ +--------+
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* ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail
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* | Module | | Module | | Module |
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* | [0] | | [1] | | [N-1] |
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* +--------+ +--------+ +--------+
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* For the 1st memory module:
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* net source is the configuration chain head of the primitive module
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* net sink is the configuration chain head of the next memory module
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*
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* For the rest of memory modules:
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* net source is the configuration chain tail of the previous memory module
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* net sink is the configuration chain head of the next memory module
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*/
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for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) {
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ModuleId net_src_module_id;
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size_t net_src_instance_id;
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ModulePortId net_src_port_id;
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ModuleId net_sink_module_id;
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size_t net_sink_instance_id;
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ModulePortId net_sink_port_id;
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if (0 == mem_index) {
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/* Find the port name of configuration chain head */
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std::string src_port_name = generate_sram_port_name(circuit_lib, memory_models[mem_index], sram_orgz_type, SPICE_MODEL_PORT_INPUT);
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net_src_module_id = parent_module;
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net_src_instance_id = 0;
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net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_configuration_chain_head_name();
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net_sink_module_id = memory_modules[mem_index];
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net_sink_instance_id = memory_instances[mem_index];
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net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
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} else {
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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net_src_module_id = memory_modules[mem_index - 1];
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net_src_instance_id = memory_instances[mem_index - 1];
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net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_configuration_chain_head_name();
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net_sink_module_id = memory_modules[mem_index];
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net_sink_instance_id = memory_instances[mem_index];
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net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
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}
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/* Get the pin id for source port */
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BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Get the pin id for sink port */
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BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);
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/* Port sizes of source and sink should match */
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VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Create a net and add source and sink to it */
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ModuleNetId net = module_manager.create_module_net(parent_module);
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/* Add net source */
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module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
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}
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}
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/* For the last memory module:
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* net source is the configuration chain tail of the previous memory module
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* net sink is the configuration chain tail of the primitive module
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*/
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/* Find the port name of previous memory module */
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std::string src_port_name = generate_configuration_chain_tail_name();
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ModuleId net_src_module_id = memory_modules.back();
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size_t net_src_instance_id = memory_instances.back();
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ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
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/* Find the port name of next memory module */
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std::string sink_port_name = generate_sram_port_name(circuit_lib, memory_models.back(), sram_orgz_type, SPICE_MODEL_PORT_OUTPUT);
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ModuleId net_sink_module_id = parent_module;
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size_t net_sink_instance_id = 0;
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ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
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/* Get the pin id for source port */
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BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id);
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/* Get the pin id for sink port */
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BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);
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/* Port sizes of source and sink should match */
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VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
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/* Create a net and add source and sink to it */
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ModuleNetId net = module_manager.create_module_net(parent_module);
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/* Add net source */
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module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
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}
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break;
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}
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case SPICE_SRAM_MEMORY_BANK:
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/* TODO: */
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d])Invalid type of SRAM organization!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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}
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/*********************************************************************
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* TODO:
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* Add the port-to-port connection between a logic module
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* and a memory module inside a primitive module
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*
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* Memory bank
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* -----------
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* config_bus (BL) config_bus (WL) shared_config_bugs(shared_BL/WLs)
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* | | | |
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* primitive | | | |
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* +------------------------------------------------------------+
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* | | | | | |
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* | v v v v |
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* | +----------------------------------------------------+ |
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* | | ReRAM-based Memory Module | |
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* | +----------------------------------------------------+ |
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* | | | |
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* | v v |
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* | mem_out mem_outb |
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* | |
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* +------------------------------------------------------------+
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*
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**********************************************************************/
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/********************************************************************
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* TODO:
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* Add the port-to-port connection between a memory module
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* and the configuration bus of a primitive module
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*
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* Create nets to wire the control signals of memory module to
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* the configuration ports of primitive module
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*
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@ -603,9 +801,42 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
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* The detailed config ports really depend on the type
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* of SRAM organization.
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*
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* The config_bus in the argument is the reserved address of configuration
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* bus in the parent_module for this memory module
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*
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* The configuration bus connection will depend not only
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* the design technology of the memory cells but also the
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* configuration styles of FPGA fabric.
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* Here we will branch on the design technology
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*
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* Note: this function SHOULD be called after the pb_type_module is created
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* and its child module (logic_module and memory_module) is created!
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*******************************************************************/
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void add_module_nets_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::vector<ModuleId>& memory_modules,
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const std::vector<size_t>& memory_instances,
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const e_sram_orgz& sram_orgz_type,
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const e_spice_model_design_tech& mem_tech,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitModelId>& memory_models) {
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switch (mem_tech) {
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case SPICE_MODEL_DESIGN_CMOS:
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add_module_nets_cmos_memory_config_bus(module_manager, parent_module,
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memory_modules, memory_instances,
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sram_orgz_type,
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circuit_lib, memory_models);
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break;
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case SPICE_MODEL_DESIGN_RRAM:
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/* TODO: */
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d])Invalid type of memory design technology !\n",
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__FILE__, __LINE__);
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exit(1);
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}
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}
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/********************************************************************
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* TODO:
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@ -65,4 +65,13 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& logic_model);
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void add_module_nets_memory_config_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::vector<ModuleId>& memory_modules,
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const std::vector<size_t>& memory_instances,
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const e_sram_orgz& sram_orgz_type,
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const e_spice_model_design_tech& mem_tech,
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const CircuitLibrary& circuit_lib,
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const std::vector<CircuitModelId>& memory_models);
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#endif
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@ -140,10 +140,6 @@ void print_verilog_primitive_block(std::fstream& fp,
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add_sram_ports_to_module_manager(module_manager, primitive_module,
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circuit_lib, sram_model, cur_sram_orgz_info->type,
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num_config_bits);
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/* Add ports only visible during formal verification to the module */
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add_formal_verification_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model,
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std::string(verilog_formal_verification_preproc_flag),
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num_config_bits);
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}
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/* Find the module id in the module manager */
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@ -160,6 +156,13 @@ void print_verilog_primitive_block(std::fstream& fp,
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std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix));
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ModuleId memory_module = module_manager.find_module(memory_module_name);
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/* Vectors to record all the memory modules have been added
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* They are used to add module nets of configuration bus
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*/
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std::vector<ModuleId> memory_modules;
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std::vector<size_t> memory_instances;
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std::vector<CircuitModelId> memory_models;
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/* If there is no memory module required, we can skip the assocated net addition */
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if (ModuleId::INVALID() != memory_module) {
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size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module);
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@ -171,8 +174,19 @@ void print_verilog_primitive_block(std::fstream& fp,
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logic_module, logic_instance_id,
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memory_module, memory_instance_id,
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circuit_lib, primitive_model);
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/* TODO: Add nets to connect configuration ports from memory module to primitive module */
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/* TODO: Add nets to connect formal verification ports from memory module to primitive module */
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/* Record memory-related information */
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memory_modules.push_back(memory_module);
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memory_instances.push_back(memory_instance_id);
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memory_models.push_back(sram_model);
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}
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/* Add all the nets to connect configuration ports from memory module to primitive modules
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* This is a one-shot addition that covers all the memory modules in this primitive module!
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*/
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if (false == memory_modules.empty()) {
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add_module_nets_memory_config_bus(module_manager, primitive_module,
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memory_modules, memory_instances,
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cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model),
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circuit_lib, memory_models);
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}
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/* Write the verilog module */
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