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plugged in the refactored wire Verilog generation

This commit is contained in:
tangxifan 2019-09-12 20:56:30 -06:00
parent 2b829238b5
commit c20e182484
2 changed files with 4 additions and 3 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -3349,9 +3349,11 @@ void dump_verilog_submodules(ModuleManager& module_manager,
print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
/* 3. Hardwires */
/*
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n");
dump_verilog_submodule_wires(verilog_dir, submodule_dir, Arch.num_segments, Arch.Segments,
Arch.spice->num_spice_model, Arch.spice->spice_models);
*/
/* Create a vector of segments. TODO: should come from DeviceContext */
std::vector<t_segment_inf> L_segment_vec;
for (int i = 0; i < Arch.num_segments; ++i) {

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp
View File

@ -175,8 +175,7 @@ void print_verilog_submodule_wires(ModuleManager& module_manager,
std::vector<t_segment_inf> routing_segments,
const std::string& verilog_dir,
const std::string& submodule_dir) {
/* TODO: remove .bak when it is ready to be plugged in */
std::string verilog_fname(submodule_dir + wires_verilog_file_name + ".bak");
std::string verilog_fname(submodule_dir + wires_verilog_file_name);
/* Create the file stream */
std::fstream fp;
@ -229,8 +228,8 @@ void print_verilog_submodule_wires(ModuleManager& module_manager,
/* Add fname to the linked list */
/* Uncomment this when it is ready to be plugged in
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
*/
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
return;
}