plugged in the refactored wire Verilog generation
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@ -3349,9 +3349,11 @@ void dump_verilog_submodules(ModuleManager& module_manager,
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print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
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/* 3. Hardwires */
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/*
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vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n");
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dump_verilog_submodule_wires(verilog_dir, submodule_dir, Arch.num_segments, Arch.Segments,
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Arch.spice->num_spice_model, Arch.spice->spice_models);
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*/
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/* Create a vector of segments. TODO: should come from DeviceContext */
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std::vector<t_segment_inf> L_segment_vec;
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for (int i = 0; i < Arch.num_segments; ++i) {
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@ -175,8 +175,7 @@ void print_verilog_submodule_wires(ModuleManager& module_manager,
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std::vector<t_segment_inf> routing_segments,
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const std::string& verilog_dir,
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const std::string& submodule_dir) {
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/* TODO: remove .bak when it is ready to be plugged in */
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std::string verilog_fname(submodule_dir + wires_verilog_file_name + ".bak");
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std::string verilog_fname(submodule_dir + wires_verilog_file_name);
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/* Create the file stream */
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std::fstream fp;
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@ -229,8 +228,8 @@ void print_verilog_submodule_wires(ModuleManager& module_manager,
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/* Add fname to the linked list */
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/* Uncomment this when it is ready to be plugged in
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submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
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*/
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submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
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return;
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}
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