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light modification on Verilog Mux generation and start refactoring memory Verilog generation

This commit is contained in:
tangxifan 2019-09-13 12:22:57 -06:00
parent d8b9349066
commit 56f40cf46c
5 changed files with 126 additions and 10 deletions
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93
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp Normal file
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@ -0,0 +1,93 @@
/*********************************************************************
* This file includes functions to generate Verilog submodules for
* the memories that are affiliated to multiplexers and other programmable
* circuit models, such as IOPADs, LUTs, etc.
********************************************************************/
#include <string>
#include <algorithm>
#include "util.h"
#include "vtr_assert.h"
/* Device-level header files */
#include "mux_graph.h"
#include "module_manager.h"
#include "physical_types.h"
#include "vpr_types.h"
#include "mux_utils.h"
/* FPGA-X2P context header files */
#include "spice_types.h"
#include "fpga_x2p_naming.h"
#include "fpga_x2p_utils.h"
/* FPGA-Verilog context header files */
#include "verilog_global.h"
#include "verilog_writer_utils.h"
#include "verilog_memory.h"
void print_verilog_submodule_memories(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
/* TODO: Generate modules into a .bak file now. Rename after it is verified */
std::string verilog_fname(submodule_dir + memories_verilog_file_name);
verilog_fname += ".bak";
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_handler(fp);
/* Print out debugging information for if the file is not opened/created properly */
vpr_printf(TIO_MESSAGE_INFO,
"Creating Verilog netlist for memories (%s) ...\n",
verilog_fname.c_str());
print_verilog_file_header(fp, "Memories used in FPGA");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create the memory circuits for the multiplexer */
for (auto mux : mux_lib.muxes()) {
const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
CircuitModelId mux_model = mux_lib.mux_circuit_model(mux);
/* Create a Verilog module for the memories used by the multiplexer */
/* Bypass the non-MUX circuit models (i.e., LUTs).
* They should be handled in a different way
* Memory circuits of LUT includes both regular and mode-select ports
*/
if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) {
continue;
}
}
/* Create the memory circuits for non-MUX circuit models.
* In this case, the memory modules are designed to interface
* the mode-select ports
*/
for (const auto& model : circuit_lib.models()) {
/* Bypass MUXes, they have already been considered */
if (SPICE_MODEL_MUX == circuit_lib.model_type(model)) {
continue;
}
/* Bypass those modules without any SRAM ports */
std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(model, SPICE_MODEL_PORT_SRAM, true);
if (0 == sram_ports.size()) {
continue;
}
/* Create a Verilog module for the memories used by the circuit model */
}
/* Close the file stream */
fp.close();
/* TODO: Add fname to the linked list when debugging is finished */
/*
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
*/
}

22
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h Normal file
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@ -0,0 +1,22 @@
/***********************************************
* Header file for verilog_memory.cpp
**********************************************/
#ifndef VERILOG_MEMORY_H
#define VERILOG_MEMORY_H
/* Include other header files which are dependency on the function declared below */
#include <fstream>
#include "circuit_library.h"
#include "mux_graph.h"
#include "mux_library.h"
#include "module_manager.h"
void print_verilog_submodule_memories(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);
#endif

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
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@ -1856,11 +1856,11 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* submodule_dir) {
const std::string& verilog_dir,
const std::string& submodule_dir) {
/* TODO: Generate modules into a .bak file now. Rename after it is verified */
std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name));
std::string verilog_fname(submodule_dir + muxes_verilog_file_name);
verilog_fname += ".bak";
/* Create the file stream */
@ -1900,7 +1900,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph);
}
/* Close the file steam */
/* Close the file stream */
fp.close();
/* TODO:
@ -1915,7 +1915,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
/* TODO: Add fname to the linked list when debugging is finished */
/*
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
*/
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h
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@ -17,7 +17,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* submodule_dir);
const std::string& verilog_dir,
const std::string& submodule_dir);
#endif

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
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@ -47,6 +47,7 @@
#include "verilog_essential_gates.h"
#include "verilog_decoders.h"
#include "verilog_lut.h"
#include "verilog_memory.h"
#include "verilog_wire.h"
#include "verilog_submodules.h"
@ -3110,7 +3111,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
const std::vector<t_segment_inf>& routing_segments,
const std::string& verilog_dir,
const std::string& submodule_dir) {
std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name + ".bak");
std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name);
/* Create the file stream */
std::fstream fp;
@ -3199,8 +3200,7 @@ void dump_verilog_submodules(ModuleManager& module_manager,
dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch,
switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info,
verilog_dir, submodule_dir);
print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir));
print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
@ -3220,6 +3220,7 @@ void dump_verilog_submodules(ModuleManager& module_manager,
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n");
dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch,
switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
/* 5. Dump decoder modules only when memory bank is required */
dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir);