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add reserved BLB/WL port naming

This commit is contained in:
tangxifan 2019-09-22 12:16:43 -06:00
parent 1e4177067d
commit 2c4372c506
4 changed files with 35 additions and 10 deletions
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20
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -282,3 +282,23 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
port_name += "_";
return port_name;
}
/*********************************************************************
* Generate the port name for a reserved sram port, i.e., BLB/WL port
* When port_type is BLB, a string denoting to the reserved BLB port is generated
* When port_type is WL, a string denoting to the reserved WL port is generated
*
* DO NOT put any SRAM organization check codes HERE!!!
* Even though the reserved BLB/WL ports are used by RRAM-based FPGA only,
* try to keep this function does simple job.
* Check codes should be added outside, when print the ports to files!!!
*********************************************************************/
std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type) {
VTR_ASSERT( (port_type == SPICE_MODEL_PORT_BLB) || (port_type == SPICE_MODEL_PORT_WL) );
if (SPICE_MODEL_PORT_BLB == port_type) {
return std::string("reserved_blb");
}
return std::string("reserved_wl");
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
View File

@ -67,4 +67,6 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
const size_t& pin_id,
const bool& for_top_netlist);
std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp
View File

@ -36,7 +36,7 @@ std::vector<CircuitPortId> find_switch_block_global_ports(const RRGSB& rr_gsb,
/* Get the model, and try to add to the sub_model list */
CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model;
/* Make sure it is a valid id */
VTR_ASSERT( CircuitModelId::INVALID() == switch_circuit_model );
VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model );
/* Get the model, and try to add to the sub_model list */
if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) {
/* Not yet in the list, add it */

21
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -2279,15 +2279,20 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
/* Add configuration ports */
/* TODO: Reserved sram ports */
/*
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_reserved_conf_bits_lsb(),
rr_gsb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
/* Check: this SRAM organization type must be memory-bank ! */
VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type );
/* Add a reserved BLB port to the module */
std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB);
BasicPort blb_module_port(blb_port_name, rr_gsb.get_sb_num_reserved_conf_bits());
module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add a reserved BLB port to the module */
std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL);
BasicPort wl_module_port(wl_port_name, rr_gsb.get_sb_num_reserved_conf_bits());
module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT);
}
*/
/* TODO: Normal sram ports */
/*
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
@ -4143,13 +4148,11 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir,
subckt_dir, unique_mirror, explicit_port_mapping);
/*
print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib,
rr_switches,
cur_sram_orgz_info, std::string(verilog_dir),
std::string(subckt_dir), unique_mirror,
explicit_port_mapping);
*/
}
/* Restore sram_orgz_info to the base */