bug fix for IO=1

2019-09-19 15:43:25 -06:00 · 2019-09-19 15:43:25 -06:00 · 0ff0c8cf06
parent 4e7af5cdc5
commit 0ff0c8cf06
1 changed files with 1 additions and 1 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
@ -653,7 +653,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,
  }

  /* Dump ports only visible during formal verification*/
-  if (0 < (cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1
+  if (0 < (cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] 
           - cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy])) {
    fprintf(fp, "\n");
    fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);