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Fix verilog generation for direct connexion from directlist

This commit is contained in:
AurelienUoU 2019-09-25 16:44:00 -06:00
parent feddcbcb21
commit a35e2936b2
2 changed files with 3 additions and 4 deletions
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3
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c
View File

@ -548,7 +548,6 @@ void init_check_arch_spice_models(t_arch* arch,
get_default_spice_model(SPICE_MODEL_WIRE,
arch->spice->num_spice_model,
arch->spice->spice_models);
continue;
} else {
arch->Directs[i].spice_model =
find_name_matched_spice_model(arch->Directs[i].spice_model_name,
@ -562,7 +561,7 @@ void init_check_arch_spice_models(t_arch* arch,
arch->Directs[i].spice_model_name,
arch->Directs[i].name);
exit(1);
} else if (SPICE_MODEL_CHAN_WIRE != arch->Directs[i].spice_model->type) {
} else if (SPICE_MODEL_WIRE != arch->Directs[i].spice_model->type) {
vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model(%s) type of CLB to CLB Direct Connection (name=%s)! Should be chan_wire!\n",
__FILE__ , __LINE__,
arch->Directs[i].spice_model_name,

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -926,7 +926,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp,
exit(1);
}
for (ipin = 0; ipin < cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index; ipin++) {
for (ipin = 0; ipin < 1 + cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index; ipin++) {
/* Update pin index and get the side of the pins on grids */
cur_from_clb_pin_index = cur_direct->from_clb_pin_start_index + ipin;
cur_to_clb_pin_index = cur_direct->to_clb_pin_start_index + ipin;
@ -950,7 +950,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp,
dump_verilog_toplevel_one_grid_side_pin_with_given_index(fp, IPIN,
cur_to_clb_pin_index,
cur_to_clb_pin_side,
to_grid_x, from_grid_y,
to_grid_x, to_grid_y,
FALSE);
fprintf(fp, ");\n");