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Buggy version but need help on debugging

This commit is contained in:
Baudouin Chauviere 2019-10-01 14:49:42 -06:00
parent d5ebe66ad9
commit 633a12ee08
3 changed files with 15 additions and 9 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -2473,7 +2473,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordina
/* Give a coordinator of a rr switch block, and return its unique mirror */
const RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const {
assert(validate_coordinator_edge(coordinator));
assert(validate_coordinator(coordinator));
size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()];
return get_sb_unique_module(sb_unique_module_id);
}

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -1319,15 +1319,20 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
/* Quote Routing structures: Channels */
if (TRUE == compact_routing_hierarchy ) {
fprintf(fp, "//TEST1\n");
dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
} else {
fprintf(fp, "//TEST2\n");
dump_compact_verilog_defined_channels(fp, is_explicit_mapping);
dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping);
}
/* Quote Routing structures: Switch Boxes */
if (TRUE == compact_routing_hierarchy ) {
fprintf(fp, "//TEST3\n");
dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping);
} else {
fprintf(fp, "//TEST4\n");
dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/
}

17
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -2200,7 +2200,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sram_lsb,
cur_sram_msb,
VERILOG_PORT_CONKT, is_explicit_mapping);
VERILOG_PORT_CONKT,
false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2297,7 +2298,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
/* Print the definition of subckt*/
fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name());
/* dump global ports */
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) {
if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) {
fprintf(fp, ",\n");
}
@ -2336,9 +2337,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE, is_explicit_mapping); /* Dump the direction of the port ! */
rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow,
TRUE, false); /* Dump the direction of the port ! */
}
}
@ -2366,7 +2367,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_conf_bits_lsb(),
rr_gsb.get_sb_conf_bits_msb(),
VERILOG_PORT_INPUT, is_explicit_mapping);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -2569,7 +2570,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info->conf_bits_lsb,
cur_sb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT, is_explicit_mapping);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}
@ -3861,7 +3862,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_cb_info->conf_bits_lsb,
cur_cb_info->conf_bits_msb - 1,
VERILOG_PORT_INPUT, is_explicit_mapping);
VERILOG_PORT_INPUT, false);
fprintf(fp, "\n");
fprintf(fp, "`endif\n");
}