make local configuration bus generation more general
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433fc73460
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1983e56557
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@ -539,27 +539,40 @@ std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib,
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return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix);
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}
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/*********************************************************************
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* Generate the port name for a SRAM port of a circuit
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* This name is used for local wires that connecting SRAM ports
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* of a circuit model inside a Verilog/SPICE module
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* Note that the SRAM ports share the same naming
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* convention regardless of their configuration style
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*********************************************************************/
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std::string generate_local_sram_port_name(const std::string& port_prefix,
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const size_t& instance_id,
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const e_spice_model_port_type& port_type) {
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std::string port_name = port_prefix + std::string("_") + std::to_string(instance_id) + std::string("_");
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if (SPICE_MODEL_PORT_INPUT == port_type) {
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port_name += std::string("out");
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} else {
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VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type );
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port_name += std::string("outb");
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}
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return port_name;
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}
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/*********************************************************************
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* Generate the port name for a SRAM port of a routing multiplexer
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* This name is used for local wires that connecting SRAM ports
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* of routing multiplexers inside a Verilog/SPICE module
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* Note that the SRAM ports of routing multiplexers share the same naming
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* convention regardless of their configuration style
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*********************************************************************/
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**********************************************************************/
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std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model,
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const size_t& mux_size,
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const size_t& mux_instance_id,
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const e_spice_model_port_type& port_type) {
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std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_");
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if (SPICE_MODEL_PORT_INPUT == port_type) {
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postfix += std::string("out");
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} else {
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VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type );
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postfix += std::string("outb");
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}
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return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix);
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std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string());
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return generate_local_sram_port_name(prefix, mux_instance_id, port_type);
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}
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@ -103,6 +103,10 @@ std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib,
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const size_t& bus_id,
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const bool& inverted);
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std::string generate_local_sram_port_name(const std::string& port_prefix,
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const size_t& instance_id,
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const e_spice_model_port_type& port_type);
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std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model,
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const size_t& mux_size,
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@ -2449,9 +2449,9 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager,
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/* Create port-to-port map */
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std::map<std::string, BasicPort> mem_port2port_name_map;
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/* Link input port to Switch block configuration bus */
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/* TODO: Link input port to Switch block configuration bus */
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/* Link output port to MUX configuration port */
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/* TODO: Link output port to MUX configuration port */
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/* Print an instance of the MUX Module */
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print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----"));
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@ -776,59 +776,61 @@ void print_verilog_local_sram_wires(std::fstream& fp,
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* ports of a CMOS (SRAM-based) routing multiplexer
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* This port is supposed to be used locally inside a Verilog/SPICE module
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*
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* The following shows a few representative examples:
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*
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* For standalone configuration style:
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* ------------------------------------
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* No bus needed
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*
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* For configuration-chain configuration style:
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* --------------------------------------------
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* Configuration chain-style
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* -------------------------
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* wire [0:N] config_bus
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*
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* Module Port
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* |
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* v
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* bus_port --------+----------------+----> ...
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* | |
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* sram_outputs v v
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* +-----------+ +-----------+
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* | Memory | | Memory |
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* | Module[0] | | Module[1] | ...
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* +-----------+ +-----------+
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* | |
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* v v
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* +-----------+ +-----------+
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* | Routing | | Routing |
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* | MUX [0] | | MUX[1] | ...
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* +-----------+ +-----------+
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* config_bus config_bus config_bus config_bus
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* [0] [1] [2] [N]
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* | | | |
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* v v v v
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* ccff_head ----------+ +---------+ +------------+ +----> ccff_tail
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* | ^ | ^ | ^
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* head v |tail v | v |
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* +----------+ +----------+ +----------+
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* | Memory | | Memory | | Memory |
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* | Module | | Module | ... | Module |
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* | [0] | | [1] | | [N] |
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* +----------+ +----------+ +----------+
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* | | |
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* v v v
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* +----------+ +----------+ +----------+
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* | MUX | | MUX | | MUX |
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* | Module | | Module | ... | Module |
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* | [0] | | [1] | | [N] |
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* +----------+ +----------+ +----------+
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*
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* For memory-bank configuration style:
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* ------------------------------------
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*
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* Module Port
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* |
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* v
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* bus_port --------+----------------+----> ...
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* | |
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* bl/wl/../sram_ports v v
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* +-----------+ +-----------+
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* | Memory | | Memory |
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* | Module[0] | | Module[1] | ...
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* +-----------+ +-----------+
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* | |
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* v v
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* +-----------+ +-----------+
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* | Routing | | Routing |
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* | MUX [0] | | MUX[1] | ...
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* +-----------+ +-----------+
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* Memory bank-style
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* -----------------
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* BL/WL bus --+------------+-------------------->
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* | | |
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* BL/WL v BL/WL v BL/WL v
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* +----------+ +----------+ +----------+
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* | Memory | | Memory | | Memory |
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* | Module | | Module | ... | Module |
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* | [0] | | [1] | | [N] |
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* +----------+ +----------+ +----------+
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* | | |
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* v v v
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* +----------+ +----------+ +----------+
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* | MUX | | MUX | | MUX |
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* | Module | | Module | ... | Module |
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* | [0] | | [1] | | [N] |
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* +----------+ +----------+ +----------+
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*
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*********************************************************************/
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static
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void print_verilog_cmos_mux_config_bus(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& mux_model,
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const e_sram_orgz& sram_orgz_type,
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const size_t& mux_size,
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const size_t& mux_instance_id,
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const size_t& num_conf_bits) {
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void print_verilog_local_config_bus(std::fstream& fp,
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const std::string& prefix,
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const e_sram_orgz& sram_orgz_type,
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const size_t& instance_id,
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const size_t& num_conf_bits) {
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/* Make sure we have a valid file handler*/
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check_file_handler(fp);
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@ -838,78 +840,20 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp,
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* The configuration ports of SRAM are directly wired to the ports of modules
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*/
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break;
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case SPICE_SRAM_SCAN_CHAIN: {
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/* To support chain-like configuration protocol, two configuration buses should be outputted
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case SPICE_SRAM_SCAN_CHAIN:
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case SPICE_SRAM_MEMORY_BANK: {
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/* Two configuration buses should be outputted
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* One for the regular SRAM ports of a routing multiplexer
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* The other for the inverted SRAM ports of a routing multiplexer
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*/
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BasicPort config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT),
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BasicPort config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_INPUT),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, config_port) << ";" << std::endl;
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BasicPort inverted_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT),
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BasicPort inverted_config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_OUTPUT),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_config_port) << ";" << std::endl;
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break;
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}
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case SPICE_SRAM_MEMORY_BANK: {
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/* To support memory-bank configuration, SRAM outputs are supposed to be exposed to the upper level as buses
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* In addition, the BL/WL ports should be grouped and be exposed to the upper level as buses
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*/
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/* Print configuration bus to group BL/WLs */
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BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl;
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BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl;
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/* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */
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BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl;
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BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl;
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/* Get the SRAM model of the mux_model */
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std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, mux_model);
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/* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */
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VTR_ASSERT( 1 == sram_models.size() );
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std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_BLB);
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std::vector<CircuitPortId> wlb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_WLB);
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/* Connect SRAM BL/WLs to bus */
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BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL),
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num_conf_bits);
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print_verilog_wire_connection(fp, bl_bus, mux_bl_wire, false);
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BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL),
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num_conf_bits);
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print_verilog_wire_connection(fp, wl_bus, mux_wl_wire, false);
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/* Print configuration bus to group BLBs, if the ports are available in SRAM models */
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if (0 < blb_ports.size()) {
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BasicPort blb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, true),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, blb_bus) << ";" << std::endl;
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/* Connect SRAM BLBs to bus */
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BasicPort mux_blb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BLB),
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num_conf_bits);
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print_verilog_wire_connection(fp, blb_bus, mux_blb_wire, false);
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}
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/* Print configuration bus to group WLBs, if the ports are available in SRAM models */
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if (0 < wlb_ports.size()) {
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BasicPort wlb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, true),
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num_conf_bits);
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fp << generate_verilog_port(VERILOG_PORT_WIRE, wlb_bus) << ";" << std::endl;
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/* Connect SRAM WLBs to bus */
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BasicPort mux_wlb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WLB),
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num_conf_bits);
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print_verilog_wire_connection(fp, wlb_bus, mux_wlb_wire, false);
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}
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break;
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}
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d])Invalid SRAM organization!\n",
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@ -1031,7 +975,11 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp,
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/*********************************************************************
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* Print a number of bus ports which are wired to the configuration
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* ports of a routing multiplexer
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* ports of a memory module, which consists of a number of configuration
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* memory cells, such as SRAMs.
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* Note that the configuration bus will only interface the memory
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* module, rather than the programming routing multiplexers, LUTs, IOs
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* etc. This helps us to keep clean and simple Verilog generation
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*********************************************************************/
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void print_verilog_mux_config_bus(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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@ -1050,9 +998,11 @@ void print_verilog_mux_config_bus(std::fstream& fp,
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* Currently, this is fine.
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*/
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switch (circuit_lib.design_tech_type(mux_model)) {
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case SPICE_MODEL_DESIGN_CMOS:
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print_verilog_cmos_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_conf_bits);
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case SPICE_MODEL_DESIGN_CMOS: {
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std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string());
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print_verilog_local_config_bus(fp, prefix, sram_orgz_type, mux_instance_id, num_conf_bits);
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break;
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}
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case SPICE_MODEL_DESIGN_RRAM:
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print_verilog_rram_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_reserved_conf_bits, num_conf_bits);
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break;
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