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Merge remote-tracking branch 'origin/ganesh_dev' into dev

This commit is contained in:
Ganesh Gore 2019-08-19 21:59:06 -06:00
parent aa7f3bef7f afee2229af
commit 69ffc38645
68 changed files with 86729 additions and 45 deletions
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.dockerignore Normal file
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# Ignore everything
*

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.gitignore vendored
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@ -32,7 +32,16 @@ vpr7_x2p/vpr/vpr
vpr7_x2p/printhandler/printhandlerdemo
vpr7_x2p/libarchfpga/read_arch
vpr7_x2p/pcre/pcredemo
ace2/ace
vpr7_x2p/libpcre/pcredemo
vpr7_x2p/libprinthandler/printhandlerdemo
vpr7_x2p/vpr/vpr_shell
# Some local temporary files
.vscode
*_local.bat
*_local.bat
fpga_flow/csv_rpts
tmp/
build/
message.txt

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Dockerfile
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FROM ubuntu:16.04
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
RUN echo "git clone https://github.com/LNIS-Projects/OpenFPGA.git" >> build.sh
RUN echo "cd OpenFPGA" >> build.sh
RUN echo "mkdir -p build && cd build" >> build.sh
RUN echo "cmake .. -DCMAKE_BUILD_TYPE=debug" >> build.sh
RUN echo "make" >> build.sh
RUN chmod +x build.sh
RUN ./build.sh
RUN mkdir -p /release /dev
WORKDIR /OpenFPGA
RUN cd release && git clone --single-branch --branch master https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_BUILD_TYPE=debug -DCMAKE_NO_GRAPHICS=on && make -j
RUN rm -rf /var/lib/apt/lists/*
WORKDIR /release/OpenFPGA

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local_test_folder/

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* Sub Circuit
* 1-Bit Full-Adder circuit netlist
.subckt adder inA inB Cin Cout Sumout svdd sgnd size=1
X01 nd1 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X02 nd1 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X03 nd2 inB nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
X04 nco inA nd2 svdd vpr_pmos W='size*beta*wp' L='pl'
X05 nco Cin nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
X06 nco Cin nd3 sgnd vpr_nmos W='size*wn' L='nl'
X07 nd3 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
X08 nd3 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
X09 nco inA nd4 sgnd vpr_nmos W='size*wn' L='nl'
X10 nd4 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
Xo1 nco Cout svdd sgnd inv size='size'
X11 nd5 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X12 nd5 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X13 nd5 Cin svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X14 nd6 inA nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
X15 nd7 inB nd6 svdd vpr_pmos W='size*beta*wp' L='pl'
X16 ndS Cin nd7 svdd vpr_pmos W='size*beta*wp' L='pl'
X23 nds nco nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
X24 nds nco nd8 sgnd vpr_nmos W='size*wn' L='nl'
X17 nd8 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
X18 nd8 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
X19 nd8 Cin sgnd sgnd vpr_nmos W='size*wn' L='nl'
X20 ndS Cin nd9 sgnd vpr_nmos W='size*wn' L='nl'
X21 nd9 inA n10 sgnd vpr_nmos W='size*wn' L='nl'
X22 n10 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
Xo2 nds Sumout svdd sgnd inv size='size'
.eom

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* Sub Circuits
*
* Static D Flip-flop
.subckt static_dff set rst clk D Q svdd sgnd size=1
* Input inverter
Xinv_clk clk clk_b svdd sgnd inv size=size
Xinv_set set set_b svdd sgnd inv size=size
Xinv_rst rst rst_b svdd sgnd inv size=size
Xinv_d D s1_n1 svdd sgnd inv size=size
Xcpt0 s1_n1 s1_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xset0 s1_n2 set_b svdd svdd vpr_pmos L=pl W='size*wp'
Xrst0 s1_n2 rst sgnd sgnd vpr_nmos L=nl W='size*wn'
Xinv1 s1_n2 s1_q svdd sgnd inv size=size
Xinv2 s1_q s1_n3 svdd sgnd inv size=size
Xcpt1 s1_n3 s1_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
* Stage 2
R3 s1_q s2_n1 0
Xcpt2 s2_n1 s2_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xrst1 s2_n2 rst_b svdd svdd vpr_pmos L=pl W='size*wp'
Xset1 s2_n2 set sgnd sgnd vpr_nmos L=nl W='size*wn'
Xinv4 s2_n2 Qb svdd sgnd inv size=size
Xinv5 Qb s2_n3 svdd sgnd inv size=size
Xcpt3 s2_n3 s2_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xinv_out Qb Q svdd sgnd inv size=size
.eom static_dff

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Testbench for D-type Flip-flop with set and reset
*********************************
* HSPICE Netlist *
* Author: Xifan TANG *
* Organization: EPFL,LSI *
*********************************
*
* Use Standard CMOS Technology
****** Include Technology Library ******
.lib '/home/xitang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel_crn45gs_2d5_v1d1_shrink0d9_embedded_usage.l' TOP_TT
****** Transistor Parameters ******
.param beta=2
.param nl=4e-08
.param wn=1.4e-07
.param pl=4e-08
.param wp=1.4e-07
****** Include subckt netlists: NMOS and PMOS *****
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/inv_buf_trans_gate.sp'
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.param clk_freq = 1e9
*Temperature
.temp 25
*Global nodes
.global vdd gnd
*Print node capacitance
.option captab
*Print waveforms
.option POST
* Parameters for measurements
.param clk2d=3e-09
.param clk_pwl=3e-09
.param clk_pwh=1.5e-08
.param slew=1e-11
.param thold=3e-09
.param vsp=0.9
* Parameters for Measuring Slew
.param slew_upper_threshold_pct_rise=0.9
.param slew_lower_threshold_pct_rise=0.1
.param slew_upper_threshold_pct_fall=0.1
.param slew_lower_threshold_pct_fall=0.9
* Parameters for Measuring Delay
.param input_threshold_pct_rise=0.5
.param input_threshold_pct_fall=0.5
.param output_threshold_pct_rise=0.5
.param output_threshold_pct_fall=0.5
Xdff[0] set rst clk d q vdd gnd static_dff
Vsupply vdd gnd 'vsp'
*Stimulates
vset set gnd 0
vrst rst gnd 0
vclk_in clk gnd pulse (0 vsp '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq' '1/clk_freq')
* Measuring Clk2Q, Setup Time and Hold Time
vdata D gnd pulse (0 vsp '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '2*0.4875/clk_freq' '2/clk_freq')
*Simulation
.tran 1e-15 '10/clk_freq'
.meas tran slew_q trig v(Q) val='slew_lower_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
+ targ v(Q) val='slew_upper_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
.meas tran clk2q trig v(CLK) val='input_threshold_pct_fall*vsp' rise=2
+ targ v(Q) val='output_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
.end TSPC Flip-flop with set and reset

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* Sub Circuit
* OR2 gate
.subckt or2 in0 in1 out svdd sgnd size=1
Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='size*beta*wp'
Xp1 ntwk_n0 in1 ntwk_n1 svdd vpr_pmos L=pl W='size*beta*wp'
Xn0 ntwk_n1 in0 sgnd sgnd vpr_nmos L=nl W='wn*size'
Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size'
.eom
* AND2 gate
.subckt and2 in0 in1 out svdd sgnd size=1
Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='wp*size*beta'
Xp1 ntwk_n0 in1 svdd svdd vpr_pmos L=pl W='wp*size*beta'
Xn0 ntwk_n0 in0 ntwk_n1 sgnd vpr_nmos L=nl W='wn*size'
Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size'
.eom

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* Sub Circuit
* IO pads
* When direction = 0, pad <= dout
* When direction = 1, pad => din
.subckt iopad zin dout din pad direction direction_inv svdd sgnd
Xbuf0 pad din_inter svdd sgnd buf size=2
Xbuf1 dout pad_inter svdd sgnd buf size=2
*Xinv0 direction direction_inv svdd sgnd inv size=1
Xcpt0 din_inter din direction direction_inv svdd sgnd cpt
Xcpt1 pad_inter pad direction_inv direction svdd sgnd cpt
.eom iopad

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* Sub Circuit
* SRAM
* Input to force write the stored bit
.subckt sram6T in out outb svdd sgnd size=1
Xinv0 loop_out loop_outb svdd sgnd inv size=size
Xinv1 loop_outb loop_out svdd sgnd inv size=size
Xout_pt loop_out out svdd sgnd svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xoutb_pt loop_outb outb svdd sgnd svdd sgnd cpt
Rin in loop_out 0
.eom sram6T

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//------ Module: sram6T_blwl -----//
//------ Verilog file: sram.v -----//
//------ Author: Xifan TANG -----//
module adder(
input [0:0] a, // Input a
input [0:0] b, // Input b
input [0:0] cin, // Input cin
output [0:0] cout, // Output carry
output [0:0] sumout // Output sum
);
//wire[1:0] int_calc;
//assign int_calc = a + b + cin;
//assign cout = int_calc[1];
//assign sumout = int_calc[0];
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

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//-----------------------------------------------------
// Design Name : static_dff
// File Name : ff.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//------ Include defines: preproc flags -----
`include "./SRC/fpga_defines.v"
module static_dff (
/* Global ports go first */
input set, // set input
input reset, // Reset input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset or posedge set)
if (reset) begin
q_reg <= 1'b0;
end else if (set) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
// Wire q_reg to Q
assign Q = q_reg;
endmodule //End Of Module static_dff
//-----------------------------------------------------
// Design Name : scan_chain_dff
// File Name : ff.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
module sc_dff (
/* Global ports go first */
input set, // set input
input reset, // Reset input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset or posedge set)
if (reset) begin
q_reg <= 1'b0;
end else if (set) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~Q;
endmodule //End Of Module static_dff
//-----------------------------------------------------
// Design Name : scan_chain_dff compact
// File Name : ff.v
// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture
// Coder : Xifan TANG
//-----------------------------------------------------
module sc_dff_compact (
/* Global ports go first */
input reset, // Reset input
//input set, // set input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset /*or posedge set*/)
if (reset) begin
q_reg <= 1'b0;
//end else if (set) begin
// q_reg <= 1'b1;
end else begin
q_reg <= D;
end
/*
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~Q;
*/
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule //End Of Module static_dff

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//-----------------------------------------------------
// Design Name : testbench for static_dff
// File Name : ff_tb.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module static_dff_tb;
// voltage sources
wire set;
reg reset;
reg clk;
reg D;
wire Q;
// Parameters
parameter clk_period = 2; // [ns] a full clock period
parameter half_clk_period = clk_period / 2; // [ns] a half clock period
parameter d_period = 2 * clk_period; // [ns] two clock period
parameter reset_period = 8 * clk_period; // [ns] a full clock period
// Unit Under Test
static_dff U0 (set, reset, clk, D, Q);
// Voltage stimuli
// Reset : enable in the first clock cycle and then disabled
initial
begin
reset = 1'b1;
#clk_period reset = ~reset;
end
always
begin
#reset_period reset = ~reset;
end
// set : alway disabled
assign set = 1'b0;
// clk: clock generator
initial
begin
clk = 1'b0;
end
always
begin
#half_clk_period clk = ~clk;
end
// D: input, flip every two clock cycles
initial
begin
D = 1'b0;
end
always
begin
#d_period D = ~D;
end
// Q is an output
//
endmodule

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//------ Module: iopad -----//
//------ Verilog file: io.v -----//
//------ Author: Xifan TANG -----//
module iopad(
//input zin, // Set output to be Z
input outpad, // Data output
output inpad, // Data input
inout pad, // bi-directional pad
input en // enable signal to control direction of iopad
//input direction_inv // enable signal to control direction of iopad
);
//----- when direction enabled, the signal is propagated from pad to din
assign inpad = en ? pad : 1'bz;
//----- when direction is disabled, the signal is propagated from dout to pad
assign pad = en ? 1'bz : outpad;
endmodule

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//-----------------------------------------------------
// Design Name : testbench for logic blocks
// File Name : lb_tb.v
// Function : Configurable logic block
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module lb_tb;
// Parameters
parameter SIZE_IN = 40; //---- MUX input size
parameter SIZE_OUT = 10; //---- MUX input size
parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size
parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size
parameter prog_clk_period = 1; // [ns] half clock period
parameter op_clk_period = 1; // [ns] half clock period
parameter config_period = 2 * prog_clk_period; // [ns] One full clock period
parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period
// Ports
wire [0:SIZE_IN-1] lb_in;
wire [0:SIZE_IN-1] lb_out;
wire lb_clk;
wire [0:SIZE_RESERV_BLWL-1] reserv_bl;
wire [0:SIZE_RESERV_BLWL-1] reserv_wl;
wire [0:SIZE_BLWL-1] bl;
wire [0:SIZE_BLWL-1] wl;
wire prog_EN;
wire prog_ENb;
wire zin;
wire nequalize;
wire read;
wire clk;
wire Reset;
wire Set;
// Clocks
wire prog_clock;
wire op_clock;
// Registered port
reg [0:SIZE_IN-1] lb_in_reg;
reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg;
reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg;
reg [0:SIZE_BLWL-1] bl_reg;
reg [0:SIZE_BLWL-1] wl_reg;
reg prog_clock_reg;
reg op_clock_reg;
// Config done signal;
reg config_done;
// Temp register for rotating shift
reg temp;
// Unit under test
grid_1__1_ U0 (
zin,
nequalize,
read,
clk,
Reset,
Set,
prog_ENb,
prog_EN,
// Top inputs
lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16],
lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36],
// Top outputs
lb_out[0], lb_out[4], lb_out[8],
// Right inputs
lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17],
lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37],
// Right outputs
lb_out[1], lb_out[5], lb_out[9],
// Bottom inputs
lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18],
lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38],
// Bottom outputs
lb_out[2], lb_out[6],
// Bottom inputs
lb_clk,
// left inputs
lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19],
lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39],
// left outputs
lb_out[3], lb_out[7],
reserv_bl, reserv_wl,
bl, wl
);
// Task: assign BL and WL values
task prog_lb_blwl;
begin
@(posedge prog_clock);
// Rotate left shift
temp = reserv_bl_reg[SIZE_RESERV_BLWL-1];
//bl_reg = bl_reg >> 1;
reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2];
reserv_bl_reg[0] = temp;
end
endtask
// Task: assign inputs
task op_lb_in;
begin
@(posedge op_clock);
temp = lb_in_reg[SIZE_IN-1];
lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2];
lb_in_reg[0] = temp;
end
endtask
// Configuration done signal
initial
begin
config_done = 1'b0;
end
// Enabled during config_period, Disabled during op_period
always
begin
#config_period config_done = ~config_done;
#operating_period config_done = ~config_done;
end
// Programming clocks
initial
begin
prog_clock_reg = 1'b0;
end
always
begin
#prog_clk_period prog_clock_reg = ~prog_clock_reg;
end
// Operating clocks
initial
begin
op_clock_reg = 1'b0;
end
always
begin
#op_clk_period op_clock_reg = ~op_clock_reg;
end
// Programming and Operating clocks
assign prog_clock = prog_clock_reg & (~config_done);
assign op_clock = op_clock_reg & config_done;
// Programming Enable signals
assign prog_EN = prog_clock & (~config_done);
assign prog_ENb = ~prog_EN;
// Programming phase: BL/WL
initial
begin
// Initialize BL/WL registers
reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}};
reserv_bl_reg[0] = 1'b1;
reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}};
// Reserved BL/WL
bl_reg = {SIZE_BLWL {1'b0}};
wl_reg = {SIZE_BLWL {1'b1}};
//wl_reg[SIZE_BLWL-1] = 1'b1;
end
always wait (~config_done) // Only invoked when config_done is 0
begin
// Propagate input 1 to the output
// BL[0] = 1, WL[4] = 1
prog_lb_blwl;
end
// Operating Phase
initial
begin
lb_in_reg = {SIZE_IN {1'b0}};
lb_in_reg[0] = 1'b1; // Last bit is 1 initially
end
always wait (config_done) // Only invoked when config_done is 1
begin
/* Update inputs */
op_lb_in;
end
// Wire ports
assign lb_in = lb_in_reg;
assign reserv_bl = reserv_bl_reg;
assign reserv_wl = reserv_wl_reg;
assign bl = bl_reg;
assign wl = wl_reg;
// Constant ports
assign zin = 1'b0;
assign nequalize = 1'b1;
assign read = 1'b0;
assign clk = op_clock;
assign Reset = ~config_done;
assign Set = 1'b0;
endmodule

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//-----------------------------------------------------
// Design Name : lut6
// File Name : lut6.v
// Function : 6-input Look Up Table
// Coder : Xifan TANG
//-----------------------------------------------------
module lut6 (
input [5:0] in,
output out,
input [63:0] sram,
input [63:0] sram_inv);
assign out = sram[in];
endmodule

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//-----------------------------------------------------
// Design Name : testbench for 2-level SRAM MUX
// File Name : mux_tb.v
// Function : SRAM-based 2-level MUXes
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module cmos_mux2level_tb;
// Parameters
parameter SIZE_OF_MUX = 50; //---- MUX input size
parameter SIZE_OF_SRAM = 16; //---- MUX input size
parameter op_clk_period = 1; // [ns] half clock period
parameter operating_period = SIZE_OF_MUX * 2 * op_clk_period; // [ns] One full clock period
// voltage sources
wire [0:SIZE_OF_MUX-1] in;
wire out;
wire [0:SIZE_OF_SRAM-1] sram;
wire [0:SIZE_OF_SRAM-1] sram_inv;
// clocks
wire op_clock;
// registered ports
reg op_clock_reg;
reg [0:SIZE_OF_MUX-1] in_reg;
reg [0:SIZE_OF_SRAM-1] sram_reg;
reg [0:SIZE_OF_SRAM-1] sram_inv_reg;
// Config done signal;
reg config_done;
// Temp register for rotating shift
reg temp;
// Unit Under Test
mux_2level_size50 U0 (in, out, sram, sram_inv);
// Task: assign inputs
task op_mux_input;
begin
@(posedge op_clock);
temp = in_reg[SIZE_OF_MUX-1];
in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2];
in_reg[0] = temp;
end
endtask
// Configuration done signal
initial
begin
config_done = 1'b1;
end
// Operating clocks
initial
begin
op_clock_reg = 1'b0;
end
always
begin
#op_clk_period op_clock_reg = ~op_clock_reg;
end
// Programming and Operating clocks
assign op_clock = op_clock_reg & config_done;
// Operating Phase
initial
begin
in_reg = {SIZE_OF_MUX {1'b0}};
in_reg[0] = 1'b1; // Last bit is 1 initially
end
always wait (config_done) // Only invoked when config_done is 1
begin
/* Update inputs */
op_mux_input;
end
// Wire ports
assign in = in_reg;
assign sram[0:7] = 8'b00010000;
assign sram[8:15] = 8'b00010000;
assign sram_inv = ~sram;
endmodule

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//------ Module: sram6T_blwl -----//
//------ Verilog file: sram.v -----//
//------ Author: Xifan TANG -----//
module sram6T_blwl(
//input read,
//input nequalize,
input din, // Data input
output dout, // Data output
output doutb, // Data output
input bl, // Bit line control signal
input wl, // Word line control signal
input blb // Inverted Bit line control signal
);
//----- local variable need to be registered
reg a;
//----- when wl is enabled, we can read in data from bl
always @(bl, wl)
begin
//----- Cases to program internal memory bit
//----- case 1: bl = 1, wl = 1, a -> 0
if ((1'b1 == bl)&&(1'b1 == wl)) begin
a <= 1'b1;
end
//----- case 2: bl = 0, wl = 1, a -> 0
if ((1'b0 == bl)&&(1'b1 == wl)) begin
a <= 1'b0;
end
end
// dout is short-wired to din
assign dout = a;
//---- doutb is always opposite to dout
assign doutb = ~dout;
`ifdef ENABLE_SIGNAL_INITIALIZATION
initial begin
$deposit(a, $random);
end
`endif
endmodule
module sram6T_rram(
input read,
input nequalize,
input din, // Data input
output dout, // Data output
output doutb, // Data output
// !!! Port bit position should start from LSB to MSB
// Follow this convention for BL/WLs in each module!
input [0:2] bl, // Bit line control signal
input [0:2] wl// Word line control signal
);
//----- local variable need to be registered
//----- Modeling two RRAMs
reg r0, r1;
always @(bl[0], wl[2])
begin
//----- Cases to program r0
//----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0
if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin
r0 <= 0;
end
end
always @(bl[2], wl[0])
begin
//----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1
if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin
r0 <= 1;
end
end
always @(bl[1], wl[2])
begin
//----- Cases to program r1
//----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0
if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin
r1 <= 0;
end
end
always @( bl[2], wl[1])
begin
//----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1
if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin
r1 <= 1;
end
end
// dout is r0 AND r1
assign dout = r0 | (~r1);
//---- doutb is always opposite to dout
assign doutb = ~dout;
endmodule

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//-----------------------------------------------------
// Design Name : testbench for static_dff
// File Name : ff_tb.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module sram6T_rram_tb;
// voltage sources
wire read;
wire nequalize;
wire din;
wire dout;
wire doutb;
reg [0:2] bl;
reg [0:2] wl;
reg prog_clock;
// Parameters
parameter prog_clk_period = 2; // [ns] a full clock period
// Unit Under Test
sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl);
// Voltage stimuli
// read : alway disabled
assign read = 1'b0;
// nequalize: always disabled
assign nequalize = 1'b1;
// din: always disabled
assign din = 1'b0;
// Programming clock
initial
begin
prog_clock = 1'b0;
end
always
begin
#prog_clk_period prog_clock = ~prog_clock;
end
// Task: assign BL and WL values
task prog_blwl;
input [0:2] bl_val;
input [0:2] wl_val;
begin
@(posedge prog_clock);
bl = bl_val;
wl = wl_val;
end
endtask
// Test two cases:
// 1. Program dout to 0
// bl[0] = 1, wl[2] = 1
// bl[2] = 1, wl[0] = 1
// 2. Program dout to 1
// bl[1] = 1, wl[2] = 1
// bl[2] = 1, wl[1] = 1
initial
begin
bl = 3'b000;
wl = 3'b000;
// 1. Program dout to 0
// bl[0] = 1, wl[2] = 1
prog_blwl(3'b100, 3'b001);
// bl[2] = 1, wl[0] = 1
prog_blwl(3'b001, 3'b100);
// 2. Program dout to 1
// bl[1] = 1, wl[2] = 1
prog_blwl(3'b010, 3'b001);
// bl[2] = 1, wl[1] = 1
prog_blwl(3'b100, 3'b010);
// 3. Program dout to 0
// bl[0] = 1, wl[2] = 1
prog_blwl(3'b100, 3'b001);
// bl[2] = 1, wl[0] = 1
prog_blwl(3'b001, 3'b100);
end
// Outputs are wired to dout and doutb
endmodule

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<architecture>
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/>
<!-- <layout width="20" height="20"/> -->
<!--mrFPGA_settings-->
<!-- below is the timing parameters for a single memristor device (or so called RRAM) -->
<!--mrFPGA R="1e3" C="2.24e-17" Tdel="0"-->
<!-- below is the timing parameters for the buffers to insert in channels -->
<!--buffer R="193.5" Cin="3.66e-15" Cout="3.56e-15" Tdel="6.14e-12"/-->
<!--cblock R_opin_cblock="193.5" T_opin_cblock="6.14e-12"/-->
<!--/mrFPGA-->
<!--/mrFPGA_settings-->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="3" cmos_variation="off" rram_variation="on">
<cmos abs_variation="0.1" num_sigma="1"/>
<rram abs_variation="0.1" num_sigma="1"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-12" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="industry" transistor_type="TT" lib_path="/research/ece/lnis/CAD_TOOLS/DKITS/wibond_R90_1P4M_v1.3/models/hspice/r90es_logic_v1d3.l" nominal_vdd="1.2" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="100e-9" min_width="120e-9"/>
<pmos model_name="pch" chan_length="100e-9" min_width="120e-9"/>
<io_nmos model_name="nch_25" chan_length="100e-9" min_width="120e-9"/>
<io_pmos model_name="pch_25" chan_length="100e-9" min_width="120e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
<port type="input" prefix="in" size="1" lib_name="I"/>
<port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1" lib_name="Z"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD4BWP" prefix="INVD4BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD1BWP" prefix="INVD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD2BWP" prefix="INVD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD3BWP" prefix="INVD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD2BWP" prefix="BUFFD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD3BWP" prefix="BUFFD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD1BWP" prefix="BUFFD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="true">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="true">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<lut_input_buffer exist="on" circuit_model_name="BUFFD3BWP"/>
<!-- <lut_intermediate_buffer exist="on" circuit_model_name="BUFFD1BWP" location_map="-1-1-"/> -->
<lut_input_inverter exist="on" circuit_model_name="INVD3BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64" circuit_model_name="sram6T_rram" default_val="1"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="1" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
<port type="wl" prefix="wl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="0" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1"/>
<port type="input" prefix="Reset" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="clk" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/io.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_rram" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="3"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="45.54e-12"/>
<area grid_logic_tile_area="0"/>
<!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
<!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
<sram area="6">
<verilog organization="memory-bank" circuit_model_name="sram6T_rram" />
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="45.54e-12" mux_trans_size="1.5" buf_size="4" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</cblocks>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L4" R="106" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L2" R="121" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="147" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.§
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic
block. Note that the crossbar / local interconnect is considered part of the logic block
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="40" equivalent="true"/>
<output name="O" num_pins="10" equivalent="false"/>
<!--input name="I" num_pins="40" equivalent="true"/-->
<!--output name="O" num_pins="20" equivalent="false"/-->
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
For spice modeling: in each primitive pb_type, user should define a circuit_model_name that linkes to the
defined spice models
-->
<pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 6-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level">
<delay_constant max="2.736e-10" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="2.736e-10" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_1level">
<delay_constant max="1.0877e-09" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="1.0877e-09" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
<!--complete name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/-->
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="top">clb.clk </loc>
<loc side="right">clb.I[19:0] clb.O[4:0] </loc>
<loc side="bottom">clb.I[39:20] clb.O[9:5] </loc>
</pinlocations>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="3"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="4"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

802
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// Benchmark "TOP" written by ABC on Mon Feb 4 10:08:03 2019
module alu4 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_,
i_11_, i_12_, i_13_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
i_10_, i_11_, i_12_, i_13_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751;
assign o_0_ = ~n42;
assign o_1_ = ~n509;
assign o_2_ = ~n502;
assign o_3_ = ~n488;
assign o_4_ = ~n41;
assign o_5_ = ~n659 | ~n662 | n40 | ~n658 | n38 | n39 | n36 | n37;
assign o_6_ = ~n35;
assign o_7_ = ~n636 | ~n637 | n34 | ~n576 | n32 | n33 | n30 | n31;
assign n30 = ~i_9_ & (~n163 | n165 | n168);
assign n31 = i_9_ & n65 & n419;
assign n32 = ~i_5_ & (~n625 | (~n238 & n250));
assign n33 = i_9_ & (n66 | ~n621 | ~n622);
assign n34 = n244 | n246 | n240 | n242 | ~n630 | ~n632 | n248 | n249;
assign n35 = n278 & n279 & (~i_2_ | n277);
assign n36 = i_11_ & (~n650 | (~n266 & n360));
assign n37 = i_2_ & n361 & n272;
assign n38 = ~n71 & ~n532;
assign n39 = ~n562 & (~n648 | (~i_13_ & ~n532));
assign n40 = ~i_4_ & (~n647 | (~n59 & ~n281));
assign n41 = n473 & n472 & n471 & n470 & n469 & ~n465 & ~n459 & ~n461;
assign n42 = ~n46 & n510 & (~i_0_ | n511);
assign n43 = ~i_1_ | ~i_3_;
assign n44 = ~i_5_ | n43;
assign n45 = ~i_8_ & i_10_;
assign n46 = i_3_ & (n45 | ~n435);
assign n47 = ~n67 & (~i_6_ | ~i_10_);
assign n48 = (n521 | n52) & (n56 | n120);
assign n49 = i_1_ | n445;
assign n50 = i_11_ | n116;
assign n51 = n48 & (n49 | n50);
assign n52 = i_12_ | n116;
assign n53 = i_0_ | n225;
assign n54 = (i_11_ | n53) & (n49 | n52);
assign n55 = ~i_6_ | i_7_;
assign n56 = i_0_ | n212;
assign n57 = ~i_2_ | i_0_ | i_1_;
assign n58 = (i_6_ | n57) & (n55 | n56);
assign n59 = ~i_3_ | n225;
assign n60 = ~i_3_ | n445;
assign n61 = (~i_6_ | n60) & (~i_5_ | n59);
assign n62 = i_0_ | n63;
assign n63 = i_3_ | i_2_;
assign n64 = n62 & (~i_5_ | n63);
assign n65 = ~i_12_ & i_13_;
assign n66 = n65 & (~n613 | (i_8_ & ~n379));
assign n67 = i_6_ & n519;
assign n68 = ~n158 & (~n615 | (n67 & ~n400));
assign n69 = (i_7_ | n200) & (i_6_ | n62);
assign n70 = n69 & (i_8_ | n56);
assign n71 = ~i_12_ | n116;
assign n72 = (~i_1_ | n71) & (~i_6_ | ~n348);
assign n73 = ~i_1_ & i_6_;
assign n74 = (~i_0_ | n73) & (~i_1_ | i_5_);
assign n75 = ~n304 & ~i_9_ & ~n77;
assign n76 = i_3_ & (n75 | (~n71 & ~n98));
assign n77 = ~i_11_ | n116;
assign n78 = i_8_ | i_6_;
assign n79 = n77 | n78 | ~i_2_ | i_9_;
assign n80 = ~i_0_ | n63;
assign n81 = ~i_0_ | n195;
assign n82 = (i_7_ | n81) & (i_6_ | n80);
assign n83 = i_0_ & (n76 | ~n79 | ~n627);
assign n84 = i_3_ | ~i_11_ | n56 | ~n348;
assign n85 = n116 | n400 | ~i_3_ | i_9_;
assign n86 = n178 | ~i_5_ | n72;
assign n87 = n516 | n177 | ~n338;
assign n88 = i_9_ | n74 | n522 | n77;
assign n89 = n88 & n87 & n86 & n85 & ~n83 & n84;
assign n90 = (n99 | n157) & (n134 | n521);
assign n91 = ~i_6_ | n522;
assign n92 = n90 & (n91 | n49);
assign n93 = (~n102 | n521) & (~n67 | n157);
assign n94 = (n518 | n49) & (n520 | n400);
assign n95 = n93 & n94;
assign n96 = (~n103 | n134) & (n53 | n107);
assign n97 = n96 & (n57 | n91);
assign n98 = ~i_6_ | n272;
assign n99 = i_8_ | ~i_6_ | ~i_7_;
assign n100 = n98 & n97 & (n99 | n56);
assign n101 = i_5_ & n365;
assign n102 = ~i_6_ & n519;
assign n103 = ~i_2_ & ~i_0_ & i_1_;
assign n104 = n101 & (~n607 | (n102 & n103));
assign n105 = i_11_ | ~n166;
assign n106 = i_10_ | n304;
assign n107 = i_6_ | n522;
assign n108 = (n107 | n50) & (n105 | n106);
assign n109 = i_12_ | n113;
assign n110 = i_11_ | n113;
assign n111 = (~n67 | n109) & (n99 | n110);
assign n112 = i_11_ | i_12_;
assign n113 = i_9_ | i_13_;
assign n114 = i_3_ | i_10_ | n112 | n113;
assign n115 = i_5_ | n312;
assign n116 = i_10_ | i_13_;
assign n117 = (~i_10_ | n115) & (n116 | ~n164);
assign n118 = i_13_ & (~n600 | (~n547 & ~n548));
assign n119 = i_5_ | n515;
assign n120 = i_12_ | ~n338;
assign n121 = (n119 | n120) & (~n164 | ~n239);
assign n122 = n65 & (~n599 | (~i_3_ & ~i_11_));
assign n123 = n555 | n518 | n554;
assign n124 = n553 | n134 | n552;
assign n125 = n522 | n198 | ~n247;
assign n126 = ~n348 | ~n67 | ~n101;
assign n127 = n449 | n107 | ~n338;
assign n128 = n524 | n99 | ~n319;
assign n129 = (n544 | n546) & (n121 | n520);
assign n130 = n129 & n128 & n127 & n126 & n125 & n124 & ~n122 & n123;
assign n131 = (n107 | ~n419) & (n91 | ~n402);
assign n132 = (n171 | n151) & (n150 | n551);
assign n133 = n597 & n598 & (n545 | n550);
assign n134 = ~i_7_ | n78;
assign n135 = ~n101 | ~n239;
assign n136 = n132 & n133 & (n134 | n135);
assign n137 = i_4_ | ~i_0_ | ~i_1_;
assign n138 = i_4_ | n445;
assign n139 = (~i_6_ | n138) & (~i_7_ | n137);
assign n140 = ~n524 & ~n220 & i_2_ & ~i_8_;
assign n141 = n546 | n549;
assign n142 = n162 | n107 | n158;
assign n143 = n555 | ~n102 | n554;
assign n144 = n553 | n91 | n552;
assign n145 = (n194 | n151) & (n198 | n551);
assign n146 = (n134 | n543) & (n547 | n550);
assign n147 = n146 & n145 & n144 & n143 & n141 & n142;
assign n148 = (n171 | n551) & (n99 | n543);
assign n149 = n595 & n596 & (n545 | n549);
assign n150 = ~i_5_ | n201;
assign n151 = ~n65 | ~n264;
assign n152 = n148 & n149 & (n150 | n151);
assign n153 = (n99 | ~n402) & (n91 | ~n419);
assign n154 = (n544 | n547) & (n172 | n198);
assign n155 = n593 & n594 & (n542 | n546);
assign n156 = n154 & n155 & (n91 | n135);
assign n157 = ~i_0_ | n212;
assign n158 = ~i_5_ | n312;
assign n159 = n158 | n157 | n134;
assign n160 = n115 | n99 | ~n103;
assign n161 = i_2_ | n312;
assign n162 = ~i_10_ | ~n319;
assign n163 = n161 | n162 | ~i_5_ | n91;
assign n164 = ~i_5_ & i_3_ & i_4_;
assign n165 = n164 & ~n77 & i_1_ & ~i_7_;
assign n166 = ~i_12_ & ~i_13_;
assign n167 = i_10_ & i_11_;
assign n168 = n166 & n167 & (~n159 | ~n160);
assign n169 = (n542 | n545) & (n541 | n150);
assign n170 = (n107 | n135) & (~n446 | n544);
assign n171 = i_3_ | n539;
assign n172 = ~n65 | ~n437;
assign n173 = n169 & n170 & (n171 | n172);
assign n174 = (~n446 | n542) & (n171 | n541);
assign n175 = (n544 | n545) & (n91 | n543);
assign n176 = n174 & n175 & (n172 | n150);
assign n177 = i_10_ | n522;
assign n178 = ~i_8_ | n272;
assign n179 = n177 & n178;
assign n180 = (~n460 | n591) & (n179 | ~n463);
assign n181 = n592 & (n533 | n56);
assign n182 = n106 & n98;
assign n183 = n180 & n181 & (n182 | ~n385);
assign n184 = (~n340 | n535) & (n106 | n449);
assign n185 = i_8_ | n534;
assign n186 = ~i_4_ | n212;
assign n187 = n184 & (n185 | n186);
assign n188 = (~n536 | n537) & (n335 | n538);
assign n189 = (n186 | n474) & (n98 | ~n101);
assign n190 = ~i_5_ | n272;
assign n191 = n188 & n189 & (n190 | ~n340);
assign n192 = (n518 | n521) & (n520 | n157);
assign n193 = n192 & (n49 | ~n102);
assign n194 = i_3_ | n214;
assign n195 = i_1_ | i_3_;
assign n196 = n194 & (~i_5_ | n195);
assign n197 = ~i_6_ | i_0_ | i_3_;
assign n198 = i_3_ | n516;
assign n199 = n198 & (i_5_ | n195);
assign n200 = i_0_ | n195;
assign n201 = i_3_ | i_6_;
assign n202 = n200 & n199 & (i_0_ | n201);
assign n203 = ~i_6_ | ~i_0_ | ~i_3_;
assign n204 = i_1_ & ~i_6_;
assign n205 = (i_2_ | ~i_6_) & (~i_7_ | n204);
assign n206 = n517 | i_6_ | n749;
assign n207 = n517 | i_1_ | i_7_;
assign n208 = i_11_ | n435;
assign n209 = n206 & n207 & (n205 | n208);
assign n210 = i_5_ | n63;
assign n211 = i_2_ | n516;
assign n212 = i_1_ | i_2_;
assign n213 = n211 & (i_5_ | n212);
assign n214 = ~i_5_ | ~i_6_;
assign n215 = (~i_5_ | n212) & (i_2_ | n214);
assign n216 = (~i_5_ | n225) & (~i_2_ | n214);
assign n217 = ~i_6_ | n445;
assign n218 = n216 & n217;
assign n219 = ~i_7_ | ~i_1_ | ~i_5_;
assign n220 = ~i_1_ & ~i_6_;
assign n221 = n219 & (~i_0_ | ~i_7_ | n220);
assign n222 = i_10_ & ~n435 & (~n218 | ~n221);
assign n223 = ~i_2_ | n516;
assign n224 = i_6_ | n445;
assign n225 = ~i_1_ | ~i_2_;
assign n226 = n223 & n224 & (i_5_ | n225);
assign n227 = n226 & (i_7_ | n74);
assign n228 = (~i_0_ | i_6_) & (~i_1_ | i_5_);
assign n229 = (i_6_ | n138) & (i_7_ | n137);
assign n230 = n73 | n119 | ~i_2_ | ~i_8_;
assign n231 = n230 & (n229 | ~n475);
assign n232 = (n53 | ~n67) & (~n103 | n518);
assign n233 = n232 & (n57 | ~n102);
assign n234 = ~i_4_ | n225;
assign n235 = ~i_4_ | n557;
assign n236 = (i_6_ | n235) & (i_8_ | n234);
assign n237 = i_4_ & (~n623 | (~i_1_ & ~n177));
assign n238 = ~n237 & (i_6_ | i_10_ | ~n536);
assign n239 = ~i_9_ & n338;
assign n240 = n239 & n164 & ~n233;
assign n241 = n406 & ~i_10_ & ~i_13_;
assign n242 = ~n119 & (~n580 | (~n92 & n241));
assign n243 = ~i_3_ & ~i_8_;
assign n244 = ~n525 & (n140 | (~n139 & n243));
assign n245 = n383 & ~i_9_ & ~i_13_;
assign n246 = ~n524 & (~n582 | (~n193 & n245));
assign n247 = ~i_11_ & i_13_;
assign n248 = n247 & (~n584 | (~n223 & ~n528));
assign n249 = n65 & (~n586 | ~n588 | ~n590);
assign n250 = n338 & i_12_;
assign n251 = n250 & (~n183 | ~n187 | ~n191);
assign n252 = ~n71 & (~n609 | ~n610 | ~n611);
assign n253 = ~n247 & (i_4_ | ~i_8_ | ~n406);
assign n254 = (~i_3_ | n208) & (~n338 | n533);
assign n255 = n253 & n254 & (n120 | ~n475);
assign n256 = ~i_7_ | i_10_;
assign n257 = i_4_ | ~n383;
assign n258 = (~i_7_ | n257) & (n256 | ~n318);
assign n259 = i_7_ & n45;
assign n260 = (i_8_ | n258) & (~n259 | n559);
assign n261 = n260 & ~n731 & (i_7_ | n255);
assign n262 = ~i_7_ | ~i_9_;
assign n263 = n262 & (i_7_ | ~i_10_);
assign n264 = i_10_ & ~i_7_ & i_8_;
assign n265 = i_12_ & (n264 | ~n548);
assign n266 = ~i_10_ | n522;
assign n267 = i_8_ | n262;
assign n268 = ~n265 & (~i_11_ | (n266 & n267));
assign n269 = (n110 | ~n243) & (n109 | ~n475);
assign n270 = ~i_4_ | n116;
assign n271 = n270 & (~i_8_ | n52);
assign n272 = ~i_7_ | i_9_;
assign n273 = ~i_4_ | n272;
assign n274 = (i_7_ | n271) & (i_13_ | n273);
assign n275 = n282 & (i_4_ | n268);
assign n276 = n556 & n638 & (i_3_ | n274);
assign n277 = n275 & n276 & (~i_13_ | n263);
assign n278 = ~n750 & (n548 | n559);
assign n279 = n644 & n645 & (i_2_ | n261);
assign n280 = ~i_6_ | ~i_9_;
assign n281 = n280 & (i_6_ | ~i_10_);
assign n282 = n332 | n116;
assign n283 = (n523 & (~i_7_ | n733)) | (i_7_ & n733);
assign n284 = i_2_ | i_13_;
assign n285 = n282 & (n283 | n284);
assign n286 = i_10_ | i_7_;
assign n287 = i_11_ | n286;
assign n288 = i_11_ | i_13_;
assign n289 = (~n166 | n287) & (n177 | n288);
assign n290 = i_8_ | n272;
assign n291 = (n288 | n290) & (~n166 | n178);
assign n292 = (n289 & (~i_6_ | n291)) | (i_6_ & n291);
assign n293 = (n523 & (~i_8_ | n733)) | (i_8_ & n733);
assign n294 = n292 & (i_13_ | n293);
assign n295 = (~i_7_ & n566) | (n565 & (i_7_ | n566));
assign n296 = i_7_ | n435;
assign n297 = n295 & (~i_6_ | ~i_11_ | n296);
assign n298 = n287 & (i_12_ | n256);
assign n299 = ~i_2_ & ~n751 & (i_6_ | ~n298);
assign n300 = ~n299 & (~i_4_ | ~n578);
assign n301 = n591 | i_2_ | ~i_4_;
assign n302 = n300 & n301 & (n182 | ~n365);
assign n303 = ~i_7_ | n280;
assign n304 = i_6_ | i_7_;
assign n305 = n303 & (~i_10_ | (~i_9_ & n304));
assign n306 = (i_6_ & ~n540) | (~n266 & (~i_6_ | ~n540));
assign n307 = ~i_4_ & (~n577 | (i_11_ & n306));
assign n308 = (n294 & (~i_3_ | n297)) | (i_3_ & n297);
assign n309 = (~i_13_ & n302) | (n281 & (i_13_ | n302));
assign n310 = ~n307 & n656 & (~i_2_ | n305);
assign n311 = n310 & n309 & n308 & n285;
assign n312 = ~i_3_ | i_4_;
assign n313 = (n312 | ~n406) & (n284 | ~n383);
assign n314 = (~i_4_ | ~n338) & (i_3_ | n120);
assign n315 = ~n247 & (~i_3_ | ~n406 | n548);
assign n316 = (~i_2_ | n530) & (~i_7_ | n313);
assign n317 = n315 & n316 & (n314 | n178);
assign n318 = i_4_ & n348;
assign n319 = ~i_11_ & n348;
assign n320 = ~n177 & (n318 | (~i_3_ & n319));
assign n321 = ~n402 | ~i_2_ | i_7_;
assign n322 = ~n319 | n563;
assign n323 = ~n383 | ~i_3_ | n266;
assign n324 = n257 | ~i_2_ | i_8_;
assign n325 = ~n65 & (i_7_ | n312 | ~n383);
assign n326 = n325 & n324 & n323 & n322 & ~n320 & n321;
assign n327 = i_11_ | ~n496 | n558 | ~n563;
assign n328 = (n317 & (~i_6_ | n326)) | (i_6_ & n326);
assign n329 = n327 & n328 & (n91 | n257);
assign n330 = ~i_11_ | n514;
assign n331 = ~n166 | ~n475;
assign n332 = ~i_4_ | i_9_;
assign n333 = (n332 | n77) & (n330 | n331);
assign n334 = ~n517 & i_3_ & i_12_;
assign n335 = i_1_ | n63;
assign n336 = ~i_11_ | ~n166;
assign n337 = (n335 | n336) & (n186 | ~n239);
assign n338 = i_11_ & ~i_13_;
assign n339 = i_4_ & (~n652 | (~n335 & n338));
assign n340 = ~i_1_ & n365;
assign n341 = i_7_ & (n334 | (n340 & n239));
assign n342 = n734 & (~i_8_ | n337);
assign n343 = (n208 | n561) & (n404 | n356);
assign n344 = (n517 | n557) & (~n45 | n59);
assign n345 = n344 & n343 & n342 & ~n341 & n333 & ~n339;
assign n346 = ~i_2_ | i_12_;
assign n347 = (~i_8_ | n59) & (n346 | ~n391);
assign n348 = i_12_ & ~i_13_;
assign n349 = n348 & (~n654 | (i_4_ & ~n335));
assign n350 = n655 & (i_8_ | ~n402 | n561);
assign n351 = ~n349 & n350 & (~i_9_ | n347);
assign n352 = ~i_8_ | i_9_;
assign n353 = (~n263 | ~n340) & (n186 | n352);
assign n354 = i_10_ | n78;
assign n355 = ~i_6_ | n352;
assign n356 = ~i_1_ | n312;
assign n357 = (n303 | n356) & (~n259 | ~n360);
assign n358 = ~n573 & (~i_4_ | i_13_ | ~n496);
assign n359 = ~n512 & (i_6_ | i_11_);
assign n360 = i_3_ & n204;
assign n361 = ~i_6_ & n419;
assign n362 = ~i_9_ | ~i_11_;
assign n363 = ~i_12_ | n362;
assign n364 = ~i_4_ | n113;
assign n365 = ~i_3_ & i_4_;
assign n366 = ~i_9_ | ~i_12_;
assign n367 = n364 & (n365 | n366);
assign n368 = (~i_9_ & n572) | (~i_13_ & (i_9_ | n572));
assign n369 = i_3_ | n111;
assign n370 = ~n166 | i_2_ | n98;
assign n371 = (~i_1_ | n280) & (n363 | ~n391);
assign n372 = (~n67 | n367) & (i_4_ | n363);
assign n373 = ~n737 & n372 & n371 & n370 & n368 & n369;
assign n374 = ~i_4_ & (~n564 | (~n107 & n167));
assign n375 = ~n736 & (~i_10_ | (~i_13_ & ~n204));
assign n376 = ~n374 & n687 & (n107 | n270);
assign n377 = n375 & n376 & (i_3_ | n108);
assign n378 = i_7_ | n516;
assign n379 = ~i_7_ | n214;
assign n380 = (n113 | n379) & (n378 | n116);
assign n381 = ~i_2_ & (~n686 | (~n270 & ~n440));
assign n382 = ~n53 & i_3_ & ~i_8_;
assign n383 = i_11_ & ~i_12_;
assign n384 = n383 & i_10_ & ~i_0_ & i_2_;
assign n385 = ~i_0_ & n365;
assign n386 = ~i_6_ & (n384 | (~n71 & n385));
assign n387 = (n56 | ~n319) & (n53 | ~n402);
assign n388 = i_0_ | n43;
assign n389 = ~n386 & n387 & (n257 | n388);
assign n390 = (~i_7_ | n81) & (~i_6_ | n80);
assign n391 = i_8_ & i_3_;
assign n392 = ~n400 & (i_7_ | n391);
assign n393 = (i_3_ & n553) | (~n241 & (~i_3_ | n553));
assign n394 = n257 & n393 & (~i_4_ | n71);
assign n395 = ~i_12_ | n572;
assign n396 = ~n65 & (i_2_ | n106 | ~n319);
assign n397 = n395 & n396 & (n394 | n107);
assign n398 = ~i_7_ | n362;
assign n399 = (i_2_ | n355) & (n204 | n178);
assign n400 = ~i_1_ | n445;
assign n401 = (~i_8_ | n400) & (~i_6_ | n60);
assign n402 = i_10_ & ~i_12_;
assign n403 = n402 & (n382 | (~i_0_ & n204));
assign n404 = i_7_ | ~n167;
assign n405 = n167 & (~n718 | (~i_8_ & ~n400));
assign n406 = ~i_11_ & i_12_;
assign n407 = n406 & (~n674 | (i_8_ & ~n53));
assign n408 = ~i_0_ | n43;
assign n409 = ~n405 & ~n407 & (n404 | n408);
assign n410 = ~n247 & (~i_1_ | i_11_ | n280);
assign n411 = n672 & (~n67 | (~n423 & n673));
assign n412 = n410 & n411 & (~n73 | n336);
assign n413 = ~n385 | ~i_6_ | ~n239;
assign n414 = ~n166 | ~i_11_ | n56;
assign n415 = n413 & n414 & (n200 | ~n423);
assign n416 = n238 & (~i_4_ | i_6_ | n177);
assign n417 = ~i_7_ & n419;
assign n418 = n417 & i_2_ & i_12_;
assign n419 = i_10_ & ~i_11_;
assign n420 = n116 | ~i_4_ | i_8_;
assign n421 = n420 & (n50 | ~n243);
assign n422 = ~n53 & (~n530 | (i_3_ & ~n208));
assign n423 = i_4_ & n239;
assign n424 = i_6_ & (n418 | (~n62 & n423));
assign n425 = (n517 | n59) & (i_4_ | n409);
assign n426 = (~i_7_ | n415) & (i_0_ | n412);
assign n427 = (n82 | n271) & (~n338 | n416);
assign n428 = (~i_1_ | ~n361) & (~n423 | n671);
assign n429 = (n157 | n421) & (n400 | ~n670);
assign n430 = ~n422 & (n56 | n120 | ~n475);
assign n431 = n430 & n429 & n428 & n427 & n426 & n425 & n333 & ~n424;
assign n432 = n183 & (~i_4_ | i_10_ | n70);
assign n433 = i_7_ | i_9_ | i_11_;
assign n434 = n191 & (n215 | n433);
assign n435 = ~i_8_ | ~i_9_;
assign n436 = i_5_ & ~n558 & (~n540 | ~n568);
assign n437 = i_10_ & n519;
assign n438 = ~i_4_ & ~n539 & (n437 | ~n568);
assign n439 = ~i_8_ | n214;
assign n440 = i_8_ | n516;
assign n441 = (n366 | n439) & (~n167 | n440);
assign n442 = ~i_12_ & (~n158 | n417 | ~n530);
assign n443 = n435 | ~i_3_ | n112;
assign n444 = ~n442 & n443 & (i_11_ | n115);
assign n445 = ~i_0_ | ~i_2_;
assign n446 = ~i_6_ & i_3_ & i_5_;
assign n447 = n383 & (~n684 | (~i_7_ & n446));
assign n448 = n406 & (~n685 | (i_7_ & ~n545));
assign n449 = i_5_ | ~n365;
assign n450 = (~n338 | n449) & (~n101 | ~n348);
assign n451 = i_5_ | n522;
assign n452 = (n80 | n440) & (n81 | n451);
assign n453 = ~i_5_ | ~n519;
assign n454 = (n453 | n81) & (n439 | n80);
assign n455 = n137 & n408;
assign n456 = ~i_0_ | n312;
assign n457 = (n379 | n456) & (n455 | n453);
assign n458 = ~i_5_ & i_0_ & i_3_;
assign n459 = n167 & (~n663 | (~n107 & n458));
assign n460 = i_4_ & ~i_0_ & ~i_2_;
assign n461 = ~n569 & (~n664 | (n239 & n460));
assign n462 = ~i_5_ & n519;
assign n463 = i_4_ & ~i_0_ & ~i_1_;
assign n464 = n462 & (~n665 | (n239 & n463));
assign n465 = ~n570 & (~n666 | (~n71 & n463));
assign n466 = ~n571 & (~n667 | (~n71 & n460));
assign n467 = n406 & (n438 | (n259 & ~n545));
assign n468 = n383 & (n436 | (~n296 & n446));
assign n469 = (n450 | n56) & (n441 | n60);
assign n470 = ~n464 & (~i_9_ | n158 | n400);
assign n471 = n702 & n701 & (n452 | n50);
assign n472 = n699 & n698 & (n457 | n366);
assign n473 = ~n740 & ~n739 & n709 & n707 & n706 & n705 & n703 & n704;
assign n474 = ~i_5_ | n352;
assign n475 = ~i_3_ & i_8_;
assign n476 = ~n56 & (i_7_ | n475);
assign n477 = (i_1_ | n537) & (n589 | n178);
assign n478 = ~n476 & n715 & (n335 | n474);
assign n479 = n477 & n478 & (i_0_ | ~i_5_);
assign n480 = ~n56 & (~i_7_ | n243);
assign n481 = n300 & (i_1_ | n359);
assign n482 = n746 & (i_5_ | n416);
assign n483 = n187 & (i_3_ | n293);
assign n484 = (n56 | ~n365) & (i_12_ | n479);
assign n485 = (n213 | n298) & (n215 | n574);
assign n486 = n716 & (i_1_ | n359 | n534);
assign n487 = n717 & (i_11_ | (n714 & n711));
assign n488 = n487 & n486 & n485 & n484 & n483 & n482 & n432 & n434;
assign n489 = ~i_7_ | n366;
assign n490 = ~i_10_ | ~i_12_;
assign n491 = n489 & ~n496 & (i_7_ | n490);
assign n492 = (n747 & (~i_5_ | n748)) | (i_5_ & n748);
assign n493 = n492 & (~i_0_ | n281);
assign n494 = i_8_ | ~i_11_;
assign n495 = ~n496 & n494 & ~i_3_ & n263;
assign n496 = i_8_ & i_12_;
assign n497 = n496 & (~n221 | ~n379);
assign n498 = (n218 | n491) & (~i_1_ | n493);
assign n499 = n726 & (~i_12_ | (n61 & n723));
assign n500 = n725 & (~i_11_ | (n719 & n722));
assign n501 = n724 & (n494 | (n227 & n378));
assign n502 = n501 & n500 & n498 & n499;
assign n503 = i_12_ | ~n475;
assign n504 = ~n46 & n503 & (i_11_ | ~n243);
assign n505 = (~n243 | ~n338) & (n113 | ~n391);
assign n506 = (~n243 | ~n247) & (~n65 | ~n475);
assign n507 = (n504 & (~i_4_ | n505)) | (i_4_ & n505);
assign n508 = n727 & n728 & (~i_13_ | ~n46);
assign n509 = n508 & n506 & n507;
assign n510 = (~i_1_ | n281) & (~i_2_ | n263);
assign n511 = (~i_5_ & ~i_10_) | (~i_9_ & (i_5_ | ~i_10_));
assign n512 = i_6_ & ~i_12_;
assign n513 = i_9_ & (n392 | (n512 & i_1_));
assign n514 = i_9_ | i_10_;
assign n515 = i_3_ | i_4_;
assign n516 = i_5_ | i_6_;
assign n517 = i_8_ | ~n419;
assign n518 = ~i_8_ | n55;
assign n519 = i_8_ & i_7_;
assign n520 = ~i_8_ | n304;
assign n521 = i_2_ | ~i_0_ | ~i_1_;
assign n522 = i_8_ | i_7_;
assign n523 = i_11_ | n514;
assign n524 = ~i_5_ | n515;
assign n525 = ~n348 | n523;
assign n526 = ~i_9_ | ~i_10_;
assign n527 = i_7_ | n526;
assign n528 = ~i_3_ | n526;
assign n529 = ~i_7_ | n526;
assign n530 = i_11_ | n262;
assign n531 = ~i_5_ | ~i_3_ | ~i_4_;
assign n532 = ~i_6_ | n332;
assign n533 = ~i_8_ | n332;
assign n534 = i_5_ | i_10_;
assign n535 = i_7_ | n534;
assign n536 = ~i_2_ & n365;
assign n537 = i_9_ | n214;
assign n538 = ~i_5_ | n332;
assign n539 = i_5_ | ~i_6_;
assign n540 = ~i_9_ | n522;
assign n541 = ~n247 | n540;
assign n542 = ~n65 | ~n259;
assign n543 = ~n239 | n449;
assign n544 = ~n247 | n296;
assign n545 = ~i_3_ | n539;
assign n546 = ~i_3_ | n516;
assign n547 = ~i_3_ | n214;
assign n548 = ~i_7_ | n435;
assign n549 = ~n247 | n548;
assign n550 = ~n65 | n266;
assign n551 = ~n247 | n267;
assign n552 = i_13_ | n115;
assign n553 = ~i_11_ | ~n402;
assign n554 = i_13_ | n158;
assign n555 = ~i_9_ | ~n406;
assign n556 = n114 & n528;
assign n557 = ~i_2_ | ~i_3_;
assign n558 = i_4_ | i_6_;
assign n559 = ~i_3_ | i_12_;
assign n560 = i_4_ | n225;
assign n561 = i_1_ | n557;
assign n562 = ~i_1_ | n63;
assign n563 = i_7_ | i_2_;
assign n564 = ~i_11_ | n490;
assign n565 = ~i_9_ | n490;
assign n566 = ~i_9_ | ~n167;
assign n567 = ~i_8_ | n286;
assign n568 = i_0_ | n557;
assign n569 = ~i_8_ | n539;
assign n570 = ~i_5_ | n522;
assign n571 = ~i_5_ | n78;
assign n572 = ~n220 | n288;
assign n573 = n243 & n319;
assign n574 = i_12_ | n272;
assign n575 = (~i_5_ & n419) | (n402 & (i_5_ | n419));
assign n576 = (~i_4_ & n729) | (n89 & (i_4_ | n729));
assign n577 = (~i_6_ & n564) | (n363 & (i_6_ | n564));
assign n578 = (i_6_ & ~n178) | (~n177 & (~i_6_ | ~n178));
assign n579 = i_10_ | i_13_ | ~n383 | n520;
assign n580 = n579 & (n233 | ~n245);
assign n581 = i_9_ | i_13_ | n99 | ~n406;
assign n582 = n581 & (n97 | ~n241);
assign n583 = n527 | ~i_3_ | n228;
assign n584 = n583 & (i_8_ | n227 | n526);
assign n585 = (n213 | n517) & (n210 | ~n361);
assign n586 = ~n222 & n585 & (n208 | n215);
assign n587 = n547 & n408 & n44 & n203;
assign n588 = (n587 | n529) & (i_0_ | n209);
assign n589 = n196 & n200 & n197;
assign n590 = (n530 | n589) & (n202 | ~n417);
assign n591 = n355 & n354;
assign n592 = (n273 | n200) & (n62 | n532);
assign n593 = n541 | n194;
assign n594 = n113 | n153 | n158;
assign n595 = ~n402 | n107 | n158;
assign n596 = ~n446 | n550;
assign n597 = ~n446 | n549;
assign n598 = n113 | n131 | n158;
assign n599 = (~n259 | n547) & (n194 | ~n519);
assign n600 = n528 & (n546 | n266);
assign n601 = n531 | ~n67 | n113;
assign n602 = n601 & (n117 | n107);
assign n603 = (n99 | n135) & (n198 | n151);
assign n604 = n602 & n603 & (n194 | n551);
assign n605 = (n108 | n119) & (n111 | n524);
assign n606 = ~n118 & n605 & (i_4_ | n556);
assign n607 = (n518 | n57) & (n53 | n520);
assign n608 = (n95 | n449) & (n92 | ~n164);
assign n609 = ~n104 & n608 & (n100 | n531);
assign n610 = (n537 | n235) & (n474 | n234);
assign n611 = (n273 | n408) & (n538 | n59);
assign n612 = n64 | ~i_6_ | i_11_;
assign n613 = n612 & (~i_10_ | n61);
assign n614 = i_10_ | ~n103 | ~n319 | n520;
assign n615 = n614 & (n58 | n162);
assign n616 = i_10_ | n157 | ~n319 | n518;
assign n617 = n616 & (n47 | n57 | n120);
assign n618 = n617 & (n520 | n521 | n50);
assign n619 = (n54 | ~n67) & (n51 | ~n102);
assign n620 = n161 | n534 | ~n102 | n120;
assign n621 = n620 & (i_4_ | n59 | ~n575);
assign n622 = ~n68 & (n115 | (n618 & n619));
assign n623 = (i_2_ | n354) & (i_10_ | n335);
assign n624 = i_11_ | n266 | n59 | n558;
assign n625 = n624 & (i_9_ | n236 | n77);
assign n626 = n355 | ~i_2_ | n71;
assign n627 = n626 & (n220 | n71 | n178);
assign n628 = n332 | i_10_ | ~n250;
assign n629 = n628 & (~n166 | n231 | n330);
assign n630 = n629 & (~i_13_ | n378 | n517);
assign n631 = n531 | n193 | ~n239;
assign n632 = ~n251 & n631 & (~n103 | n176);
assign n633 = (n156 | n521) & (n173 | n157);
assign n634 = n633 & (n152 | n53);
assign n635 = (n136 | n49) & (n147 | n57);
assign n636 = n635 & n634 & (n130 | n56);
assign n637 = ~n252 & (n400 | (n604 & n606));
assign n638 = n730 & (~i_7_ | n269);
assign n639 = ~n435 | ~i_4_ | n77;
assign n640 = n639 & (i_8_ | i_13_ | n235);
assign n641 = (i_11_ | n161) & (~n338 | ~n536);
assign n642 = n235 | ~i_8_ | i_13_;
assign n643 = n642 & (~n348 | (n533 & ~n536));
assign n644 = n312 | ~i_2_ | n263;
assign n645 = ~n732 & (i_7_ | (n640 & n641));
assign n646 = ~n563 | ~n361 | ~n496;
assign n647 = n646 & (n359 | n561);
assign n648 = (n288 | n354) & (~n166 | n355);
assign n649 = ~i_8_ | i_3_ | i_6_ | n749 | i_10_ | ~n166;
assign n650 = n649 & (~n348 | n353);
assign n651 = i_10_ | i_13_ | n749 | n494;
assign n652 = n651 & (n116 | n562);
assign n653 = i_10_ | i_8_;
assign n654 = (n286 | ~n340) & (n186 | n653);
assign n655 = n335 | i_8_ | ~n319;
assign n656 = n365 | n548 | ~i_6_ | ~i_12_;
assign n657 = ~i_3_ | ~i_9_ | ~n383 | n518;
assign n658 = n657 & (n281 | ~n496 | n560);
assign n659 = (n358 | n98) & (n346 | n303);
assign n660 = (n345 & (~i_6_ | n351)) | (i_6_ & n351);
assign n661 = (~i_1_ & n329) | (n311 & (i_1_ | n329));
assign n662 = n660 & n661 & (~i_12_ | n357);
assign n663 = (n378 | n456) & (n455 | n451);
assign n664 = (n555 | n568) & (n62 | ~n245);
assign n665 = (n388 | n555) & (n200 | ~n245);
assign n666 = (n388 | n553) & (n200 | ~n241);
assign n667 = (n553 | n568) & (n62 | ~n241);
assign n668 = (n288 | n535) & (~n166 | n190);
assign n669 = (n116 | n449) & (~n101 | n113);
assign n670 = i_10_ & (~i_7_ | (i_3_ & ~i_8_));
assign n671 = ~i_8_ | n56;
assign n672 = n741 & (~i_2_ | n303 | ~n406);
assign n673 = (i_3_ & n555) | (~n245 & (~i_3_ | n555));
assign n674 = (~i_7_ | n388) & (i_0_ | ~n67);
assign n675 = ~n383 | i_8_ | n53;
assign n676 = n675 & (n401 | n366);
assign n677 = n157 | ~i_8_ | n113;
assign n678 = n677 & (~n348 | n399);
assign n679 = n346 | i_6_ | n398;
assign n680 = n679 & (n390 | n364);
assign n681 = (~n243 | n525) & (n157 | n269);
assign n682 = n680 & n681 & (n56 | ~n573);
assign n683 = (i_7_ | n389) & (i_0_ | n397);
assign n684 = (~i_2_ | n571) & (~i_1_ | n570);
assign n685 = (~i_2_ | n569) & (~i_1_ | ~n462);
assign n686 = (n364 | n439) & (n105 | n537);
assign n687 = n288 | i_2_ | n106;
assign n688 = (n451 | n270) & (n364 | n453);
assign n689 = n211 | i_10_ | n105;
assign n690 = n689 & (~i_9_ | n536 | n564);
assign n691 = ~n381 & n690 & (~n365 | n380);
assign n692 = i_3_ | i_13_ | n293;
assign n693 = n735 & (~i_6_ | ~i_12_ | n529);
assign n694 = n285 & n692 & (~i_3_ | n693);
assign n695 = (~i_5_ & n377) | (n373 & (i_5_ | n377));
assign n696 = n695 & ~n738 & (~i_1_ | n526);
assign n697 = n564 | i_8_ | ~n458;
assign n698 = n697 & (n213 | n256 | n336);
assign n699 = n400 | ~i_10_ | n115;
assign n700 = n567 | n199 | n120;
assign n701 = n700 & (n454 | n109);
assign n702 = ~n319 | n196 | n290;
assign n703 = ~n466 & (n157 | (n668 & n669));
assign n704 = (n444 | n53) & (n217 | n565);
assign n705 = ~n467 & ~n468 & (n138 | n441);
assign n706 = (~n348 | n434) & (~n250 | n432);
assign n707 = (n538 | n71) & (n566 | n224);
assign n708 = n445 | i_5_ | n512 | n404;
assign n709 = n708 & ~n745 & (i_5_ | n431);
assign n710 = (n589 | n290) & (n202 | n177);
assign n711 = ~n480 & n710 & (n62 | n354);
assign n712 = (n185 | n335) & (n210 | n354);
assign n713 = ~n220 | ~i_5_ | i_9_;
assign n714 = n713 & n712 & (i_0_ | i_5_);
assign n715 = (n202 | n567) & (n64 | n355);
assign n716 = i_10_ | n332;
assign n717 = (i_2_ | n283) & (i_0_ | n481);
assign n718 = i_6_ | n60;
assign n719 = ~i_12_ & n718 & (i_5_ | n59);
assign n720 = n228 | ~i_3_ | i_7_;
assign n721 = n720 & (i_7_ | n408);
assign n722 = n721 & (n546 | (~i_2_ & i_7_));
assign n723 = (~i_7_ | n587) & (~i_2_ | n547);
assign n724 = ~n497 & (n226 | (n398 & n404));
assign n725 = ~i_0_ | n511;
assign n726 = n495 | n400;
assign n727 = ~n435 | ~i_3_ | n270;
assign n728 = ~n365 | ~i_8_ | ~n348;
assign n729 = ~i_5_ | n59 | ~n512 | n548;
assign n730 = ~n243 | i_7_ | n50;
assign n731 = i_7_ & (n573 | n65);
assign n732 = i_7_ & (~n643 | (~i_12_ & ~n161));
assign n733 = i_12_ | n514;
assign n734 = n560 | i_8_ | ~n167;
assign n735 = n527 | i_6_ | ~i_11_;
assign n736 = ~i_10_ & (~n572 | (n73 & n166));
assign n737 = i_2_ & i_12_ & (~n303 | ~n398);
assign n738 = ~i_1_ & (~n688 | (n166 & ~n537));
assign n739 = ~i_0_ & ~i_4_ & (n447 | n448);
assign n740 = i_0_ & (~n691 | ~n694 | ~n696);
assign n741 = i_2_ | n98 | n120;
assign n742 = i_4_ & (~n678 | (~n70 & ~n71));
assign n743 = ~i_4_ & (~n676 | (~n408 & ~n489));
assign n744 = ~n682 | n403 | n513 | n743 | ~n683 | n742;
assign n745 = i_5_ & n744;
assign n746 = n399 | ~i_4_ | ~i_5_;
assign n747 = (i_6_ & n362) | (~n167 & (~i_6_ | n362));
assign n748 = (~i_6_ & n490) | (n366 & (i_6_ | n490));
assign n749 = i_2_ & i_7_;
assign n750 = n417 & n533 & i_3_;
assign n751 = i_6_ & n574 & n433;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:25:42 2019
module apex4 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_;
wire n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209,
n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245,
n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329,
n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377,
n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389,
n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,
n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521,
n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749;
assign o_0_ = 1'b0;
assign o_1_ = ~n134;
assign o_2_ = ~n492;
assign o_3_ = ~n129;
assign o_4_ = ~n128;
assign o_5_ = ~n119;
assign o_6_ = ~n110;
assign o_7_ = ~n101;
assign o_8_ = ~n313;
assign o_9_ = ~n100;
assign o_10_ = ~n526;
assign o_11_ = ~n91;
assign o_12_ = ~n87;
assign o_13_ = ~n80;
assign o_14_ = ~n72;
assign o_15_ = ~n64;
assign o_16_ = ~n63;
assign o_17_ = ~n61;
assign o_18_ = ~n53;
assign n47 = n440 | n512;
assign n48 = n539 | n454;
assign n49 = n425 | n540;
assign n50 = n305 | n557;
assign n51 = n643 & n644 & n409 & n616 & n645 & n646 & n642 & n647;
assign n52 = n65 & (n515 | n514);
assign n53 = n47 & n48 & n49 & n50 & n51 & n52;
assign n54 = n641 & n501 & n624 & n620 & n586;
assign n55 = n314 | n591;
assign n56 = n528 | n208;
assign n57 = n425 | n558;
assign n58 = n236 | n576;
assign n59 = n545 | ~i_6_ | n531;
assign n60 = n49 & n742;
assign n61 = n48 & n54 & n55 & n56 & n57 & n58 & n59 & n60;
assign n62 = n651 & n652 & n653 & n654 & n650 & n259 & n604 & n655;
assign n63 = n54 & n62 & n50 & n47;
assign n64 = n51 & n62 & n58 & n56;
assign n65 = n190 | n543 | n514;
assign n66 = n229 | n548;
assign n67 = n443 | ~i_0_ | n419;
assign n68 = n190 | n562;
assign n69 = n656 & n247 & n657 & n621 & n658 & n599 & n659;
assign n70 = n437 & n456 & n513 & n660 & n661 & n516 & n662 & n663;
assign n71 = n504 & n505 & n506 & n507 & n508 & n509 & n510 & n511;
assign n72 = n65 & n66 & n67 & n68 & n69 & n70 & n71;
assign n73 = n664 & n597 & n556 & n264 & n358 & n391 & n434 & ~n522;
assign n74 = n360 & n517 & n399 & n518 & n519 & n520 & n521;
assign n75 = n515 | n245;
assign n76 = n440 | n558;
assign n77 = ~i_0_ | n190 | n250 | n252;
assign n78 = n430 | n419;
assign n79 = ~n332 | n345;
assign n80 = n73 & n74 & n75 & n70 & n76 & n77 & n78 & n79;
assign n81 = n634 & n596 & n350 & n468 & n130 & n665 & n666 & n667;
assign n82 = n440 | n144;
assign n83 = i_3_ | n373 | n419;
assign n84 = n190 | n575;
assign n85 = n342 | n559;
assign n86 = n182 | n575;
assign n87 = n74 & n81 & n82 & n69 & n83 & n84 & n85 & n86;
assign n88 = n560 | n575;
assign n89 = ~i_3_ | i_5_ | n440 | ~n461;
assign n90 = n345 | ~i_0_ | n250;
assign n91 = n88 & n89 & n59 & n90 & n71 & n73 & n81;
assign n92 = n570 & n193 & n202 & n199 & n588 & n589;
assign n93 = n178 & n184 & n183 & n185 & n186 & n187 & n188 & n189;
assign n94 = n141 & n155 & n160 & n164 & n172 & n122 & n173 & n174;
assign n95 = n221 & n222 & (n223 | n224);
assign n96 = n213 & n214 & n215 & n216 & n217 & n218 & n219 & n220;
assign n97 = n210 & n206 & n583 & n212 & n584 & n585 & n586 & n587;
assign n98 = n582 & n580 & ~n255 & n123 & n238 & n249 & ~n254;
assign n99 = n660 & n685 & n615 & n686 & n687 & n325 & n253 & n684;
assign n100 = n92 & n93 & n94 & n95 & n96 & n97 & n98 & n99;
assign n101 = n102 & n348 & n349 & n347 & n350 & n351 & n352 & n353;
assign n102 = n325 & n326 & n152 & n327 & n328 & n329 & n330 & n331;
assign n103 = n371 & (i_5_ | n372);
assign n104 = n369 & (n190 | n223 | n370);
assign n105 = n630 & n366 & n368 & n149 & n216 & n631;
assign n106 = n151 & n358 & n359 & n360 & n361 & n362 & n363 & n364;
assign n107 = n580 & n379 & n210 & n267 & n285 & ~n377;
assign n108 = n90 & n417 & n712 & n148 & n568 & n713;
assign n109 = n646 & n66 & n75 & n86 & n374 & ~n376;
assign n110 = n102 & n103 & n104 & n105 & n106 & n107 & n108 & n109;
assign n111 = n414 & (n415 | n416);
assign n112 = n281 & n413 & (n224 | ~n332);
assign n113 = n407 & n79 & n408 & n409 & n49 & n410 & n411 & n412;
assign n114 = n399 & n400 & n401 & n402 & n403 & n404 & n405 & n406;
assign n115 = n391 & n392 & n393 & n394 & n395 & n396 & n397 & n398;
assign n116 = n349 & n424 & n420 & n431 & n94 & n307;
assign n117 = n638 & n656 & n713 & n694 & n57 & n651;
assign n118 = n427 & n428 & n429 & n614 & n86 & n696;
assign n119 = n111 & n112 & n113 & n114 & n115 & n116 & n117 & n118;
assign n120 = n262 & n266 & n267 & n268 & n269 & n270 & n271 & n272;
assign n121 = n315 & n202 & n613 & n614;
assign n122 = n168 & n169 & (n170 | n171);
assign n123 = n88 & n231 & (n232 | n233);
assign n124 = n240 | n415 | i_0_ | ~i_2_;
assign n125 = n443 | n190 | n444;
assign n126 = n500 & n719 & n720;
assign n127 = n435 & n457 & n442 & n437 & n386 & n111 & n348 & n106;
assign n128 = n120 & n121 & n122 & n123 & n124 & n125 & n126 & n127;
assign n129 = n447 & n456 & n455 & n457 & n115 & n347 & n458 & n459;
assign n130 = n382 & n496 & (n145 | n335);
assign n131 = n640 & n494 & n495 & n505 & n504 & n619;
assign n132 = n661 & n657 & n497;
assign n133 = n603 & n48 & n68 & n720 & n279 & n187 & n602 & n741;
assign n134 = ~n499 & n97 & n112 & n130 & n131 & n132 & n133 & ~n498;
assign n135 = n339 | n542;
assign n136 = n440 | n416;
assign n137 = n166 | n541;
assign n138 = n236 | n538;
assign n139 = (n440 | n237) & (n305 | n224);
assign n140 = n679 & (n301 | n226 | n515);
assign n141 = n135 & n136 & n137 & n138 & n139 & n140;
assign n142 = n301 | n354 | n474;
assign n143 = n166 | n341;
assign n144 = n430 | n158;
assign n145 = i_6_ | i_7_;
assign n146 = n142 & n143 & (n144 | n145);
assign n147 = n422 | n467;
assign n148 = n170 | n544;
assign n149 = n342 | n367;
assign n150 = n440 | n436;
assign n151 = n166 | n365;
assign n152 = ~i_6_ | ~i_8_ | n453;
assign n153 = n422 | n546;
assign n154 = n146 & (n440 | n232 | n430);
assign n155 = n147 & n148 & n149 & n150 & n151 & n152 & n153 & n154;
assign n156 = n425 | n448;
assign n157 = n229 | n252 | n226;
assign n158 = i_5_ | n533;
assign n159 = n182 | ~n332;
assign n160 = n156 & n157 & (n158 | n159);
assign n161 = n529 | n548;
assign n162 = n425 | n546;
assign n163 = (n440 | n534) & (n423 | n454);
assign n164 = n161 & n162 & n163;
assign n165 = n182 | n430;
assign n166 = i_5_ | n240;
assign n167 = n165 | n166;
assign n168 = n240 | n223 | n208;
assign n169 = n342 | n337;
assign n170 = ~i_5_ | n533;
assign n171 = n425 | n430;
assign n172 = n553 & n554 & n167 & n286 & n555 & n556;
assign n173 = n683 & n477 & (n425 | n195);
assign n174 = n633 & n482 & n637 & n609 & n681 & n682 & n621 & n680;
assign n175 = n454 | n463;
assign n176 = n236 | n209;
assign n177 = (n166 | n559) & (n158 | n341);
assign n178 = n175 & n176 & n177;
assign n179 = n560 | n441;
assign n180 = n531 | n224;
assign n181 = n166 | n305;
assign n182 = ~i_6_ | n529;
assign n183 = n179 & n180 & (n181 | n182);
assign n184 = n295 & n294 & n563;
assign n185 = n166 | n367;
assign n186 = n529 | n531 | n472;
assign n187 = n225 | n301 | ~n332;
assign n188 = n678 & (~i_8_ | n562);
assign n189 = n675 & n676 & n269 & n76 & n362 & n624 & n677 & n50;
assign n190 = i_7_ | i_8_;
assign n191 = ~i_6_ | n543;
assign n192 = ~i_0_ | ~n469;
assign n193 = n85 & (n190 | n191 | n192);
assign n194 = i_6_ | ~i_7_;
assign n195 = n166 | n223;
assign n196 = n194 | n195;
assign n197 = n416 | n454;
assign n198 = n232 | n223;
assign n199 = n197 & (n198 | n145);
assign n200 = n166 | n566;
assign n201 = n339 | n274;
assign n202 = n200 & n201 & (n182 | n144);
assign n203 = n166 | n337;
assign n204 = n425 | n209;
assign n205 = (n158 | n233) & (n198 | n454);
assign n206 = n203 & n204 & n205;
assign n207 = n145 | n170 | ~n461;
assign n208 = ~i_6_ | n229;
assign n209 = n241 | n545;
assign n210 = n207 & (n208 | n209);
assign n211 = n223 | n339;
assign n212 = n211 | n208;
assign n213 = n440 | n209;
assign n214 = n158 | n274;
assign n215 = n236 | n572;
assign n216 = n182 | n572;
assign n217 = n415 | n211;
assign n218 = n301 | n191 | n488;
assign n219 = n182 | n211;
assign n220 = (n166 | n573) & (n532 | n145);
assign n221 = n531 | n229 | n545;
assign n222 = n59 & (n232 | ~n332 | n574);
assign n223 = ~i_2_ | n321;
assign n224 = n425 | n339;
assign n225 = i_6_ | n487;
assign n226 = ~i_1_ | n443;
assign n227 = n226 | ~i_7_ | n225;
assign n228 = i_0_ | n191 | ~n469;
assign n229 = ~i_7_ | ~i_8_;
assign n230 = n228 | n229;
assign n231 = n422 | n195;
assign n232 = ~i_5_ | n240;
assign n233 = n182 | ~n461;
assign n234 = n190 | n515 | n488;
assign n235 = n342 | n372;
assign n236 = i_6_ | n529;
assign n237 = n531 | n158;
assign n238 = n234 & n235 & (n236 | n237);
assign n239 = n321 | n577;
assign n240 = ~i_3_ | i_4_;
assign n241 = ~i_2_ | n373;
assign n242 = ~i_6_ | i_8_;
assign n243 = n239 & (n240 | n241 | n242);
assign n244 = i_6_ | n323;
assign n245 = n190 | ~n461;
assign n246 = n244 | n245;
assign n247 = n339 | n573;
assign n248 = i_3_ | i_4_ | i_6_;
assign n249 = n247 & (n229 | n248 | ~n332);
assign n250 = i_2_ | ~i_3_;
assign n251 = n250 | ~i_0_ | n225;
assign n252 = i_6_ | ~i_4_ | i_5_;
assign n253 = ~i_1_ | ~i_7_ | n250 | n252;
assign n254 = i_8_ & (~n251 | (~n430 & ~n472));
assign n255 = ~i_5_ & (~n591 | (~n422 & ~n561));
assign n256 = n425 | n436;
assign n257 = n378 | ~n461;
assign n258 = n170 | n367;
assign n259 = n208 | n558;
assign n260 = n327 & (n166 | n229 | ~n461);
assign n261 = n301 | n144;
assign n262 = n256 & n257 & n258 & n259 & n260 & n261;
assign n263 = n415 | n538;
assign n264 = n181 | n208;
assign n265 = n578 & (n301 | n241 | n444);
assign n266 = n78 & n263 & n264 & n265;
assign n267 = n592 & n593;
assign n268 = n238 & n700 & (n537 | n191);
assign n269 = n339 | n440 | ~n461;
assign n270 = n342 | n365;
assign n271 = n232 | n241 | n242;
assign n272 = n669 & n699 & n656 & n410;
assign n273 = ~n415 & (~n237 | (~n305 & ~n533));
assign n274 = n208 | ~n332;
assign n275 = n274 | n170;
assign n276 = n444 | n565;
assign n277 = n365 | ~i_4_ | i_5_;
assign n278 = n276 & n277 & (n225 | n245);
assign n279 = n232 | n372;
assign n280 = n529 | n571;
assign n281 = n342 | n159;
assign n282 = n182 | n539;
assign n283 = n691 & (n527 | n544);
assign n284 = n689 & n466 & n690 & n658 & n452 & n648 & n138 & n402;
assign n285 = n279 & n280 & n281 & n282 & n183 & n146 & n283 & n284;
assign n286 = n545 | n274;
assign n287 = n158 | n542;
assign n288 = n532 | n425;
assign n289 = n425 | n453;
assign n290 = n170 | n302 | n430;
assign n291 = n182 | n423;
assign n292 = (n532 | n454) & (n528 | n145);
assign n293 = n286 & n136 & n287 & n288 & n289 & n290 & n291 & n292;
assign n294 = n208 | n546;
assign n295 = n440 | n493;
assign n296 = n236 | n564;
assign n297 = n158 | n591;
assign n298 = n688 & (n158 | n236 | ~n332);
assign n299 = n305 | n229 | n354;
assign n300 = n294 & n295 & n296 & n297 & n298 & n299;
assign n301 = ~i_7_ | i_8_;
assign n302 = i_6_ | ~i_8_;
assign n303 = n531 | n339;
assign n304 = (n301 | n228) & (n302 | n303);
assign n305 = i_2_ | n321;
assign n306 = i_3_ | i_5_;
assign n307 = n239 & (n305 | n236 | n306);
assign n308 = n602 & n603 & n604 & n519;
assign n309 = n702 & (~i_1_ | n182 | n342);
assign n310 = n351 & n285 & n120 & n300 & n304 & n293;
assign n311 = n673 & n84 & n640 & n675 & n701 & n67;
assign n312 = n76 & n404 & n219 & n636 & n649 & n79;
assign n313 = n308 & n95 & n307 & n309 & n160 & n310 & n311 & n312;
assign n314 = i_3_ | n487;
assign n315 = n159 | n314;
assign n316 = n165 | n232;
assign n317 = n440 | n423;
assign n318 = n190 | n248 | ~n332;
assign n319 = (n236 | n536) & (n415 | n575);
assign n320 = n317 & n318 & n319;
assign n321 = i_0_ | ~i_1_;
assign n322 = n191 | n301 | n321 | i_3_;
assign n323 = i_3_ | ~i_5_;
assign n324 = n208 | n223 | n323;
assign n325 = n537 | n252;
assign n326 = n415 | n467;
assign n327 = n342 | n573;
assign n328 = n706 & (i_0_ | n443 | n419);
assign n329 = i_3_ | n566;
assign n330 = n320 & n478 & n300 & n172 & n121 & n612 & n617;
assign n331 = n705 & n218 & n403 & n257 & n150 & n187 & n583 & n704;
assign n332 = ~i_2_ & ~n426;
assign n333 = ~n170 & (~n233 | (~n301 & n332));
assign n334 = ~n430 & (~n224 | (~n314 & ~n529));
assign n335 = n342 | n241;
assign n336 = n335 | n190;
assign n337 = ~n332 | n422;
assign n338 = n337 | n232;
assign n339 = i_5_ | n527;
assign n340 = n242 | n339 | ~n461;
assign n341 = n415 | ~n461;
assign n342 = ~i_5_ | n527;
assign n343 = n341 | n342;
assign n344 = n681 & n563 & n703;
assign n345 = n229 | n444;
assign n346 = i_1_ | ~n469;
assign n347 = n243 & n344 & (n345 | n346);
assign n348 = n621 & n622 & n623 & n624 & n496 & n625 & n626 & n627;
assign n349 = n340 & n343 & n58 & n620;
assign n350 = n618 & n405 & n619;
assign n351 = n605 & n178 & n606 & n607 & n278 & n596 & n601 & n608;
assign n352 = n582 & n193 & n266;
assign n353 = n399 & n258 & n695 & n708 & n506 & n186 & n654 & n707;
assign n354 = ~i_6_ | n487;
assign n355 = n301 | n354 | ~n461;
assign n356 = ~i_4_ | ~i_5_;
assign n357 = n356 | n165;
assign n358 = n182 | n448;
assign n359 = n241 | n224;
assign n360 = n232 | n182 | n241;
assign n361 = n166 | n159;
assign n362 = n170 | n341;
assign n363 = n47 & n501 & n147;
assign n364 = n408 & n396 & n676 & n197 & n710 & n388 & n711 & n709;
assign n365 = n430 | n208;
assign n366 = n365 | n232;
assign n367 = ~n332 | n425;
assign n368 = n367 | n158;
assign n369 = n531 | n208 | n547;
assign n370 = i_6_ | n547;
assign n371 = n534 | n449;
assign n372 = n425 | ~n461;
assign n373 = ~i_0_ | ~i_1_;
assign n374 = n373 | n301 | n339;
assign n375 = (i_1_ & (~i_5_ | ~n426)) | (i_5_ & ~n426);
assign n376 = ~n454 & ~i_4_ & n375;
assign n377 = ~n195 & (~n425 | ~n449);
assign n378 = n232 | n236;
assign n379 = ~n332 | n378;
assign n380 = n241 | n557;
assign n381 = n423 | n208;
assign n382 = n166 | n590;
assign n383 = n232 | n542;
assign n384 = (n170 | n541) & (n422 | n453);
assign n385 = n716 & (~i_1_ | i_2_ | n577);
assign n386 = n380 & n381 & n382 & n383 & n384 & n385;
assign n387 = n422 | n549;
assign n388 = n355 & n357 & n628 & n629;
assign n389 = n529 | n515;
assign n390 = n387 & n388 & (n389 | n346);
assign n391 = n236 | n549;
assign n392 = n170 | n590;
assign n393 = n415 | n441;
assign n394 = n182 | n564;
assign n395 = n425 | n538;
assign n396 = n208 | n441;
assign n397 = n425 | n441;
assign n398 = n390 & n320 & n386 & n308 & n278 & n718;
assign n399 = n166 | n430 | n454;
assign n400 = n170 | n159;
assign n401 = n314 | n559;
assign n402 = n425 | n564;
assign n403 = n144 | n454;
assign n404 = n314 | n274;
assign n405 = n538 | n208;
assign n406 = n326 & n607 & n282 & n697 & n714 & n715;
assign n407 = n474 | n438;
assign n408 = n314 | n449 | ~n461;
assign n409 = n449 | n564;
assign n410 = n182 | n467;
assign n411 = n708 & n625 & (n537 | n248);
assign n412 = n613 & n698 & n710;
assign n413 = n594 & n693 & n90;
assign n414 = n301 | n430 | n252;
assign n415 = i_6_ | n301;
assign n416 = n305 | n170;
assign n417 = n415 | n453;
assign n418 = n425 | n576;
assign n419 = n225 | n229;
assign n420 = n417 & n418 & (n192 | n419);
assign n421 = n574 | ~n332 | n545;
assign n422 = ~i_6_ | n301;
assign n423 = n166 | n241;
assign n424 = n421 & (n422 | n423);
assign n425 = ~i_6_ | n190;
assign n426 = ~i_0_ | i_1_;
assign n427 = n425 | n240 | n426;
assign n428 = n354 | i_7_ | n192;
assign n429 = n229 | n241 | n244;
assign n430 = i_2_ | n373;
assign n431 = n224 | n430;
assign n432 = ~n454 & ((~n223 & ~n306) | ~n534);
assign n433 = n372 | n158;
assign n434 = n415 | n546;
assign n435 = n434 & (n229 | ~n332 | n370);
assign n436 = n223 | n545;
assign n437 = n401 & (n236 | n436);
assign n438 = n229 | n515;
assign n439 = ~i_0_ | ~i_2_;
assign n440 = i_6_ | n190;
assign n441 = n223 | n170;
assign n442 = (n438 | n439) & (n440 | n441);
assign n443 = ~i_2_ | i_3_;
assign n444 = i_6_ | n356;
assign n445 = n208 | n493;
assign n446 = (n422 | n575) & (n529 | n441);
assign n447 = n445 & n361 & n446;
assign n448 = n430 | n545;
assign n449 = ~i_6_ | ~i_7_;
assign n450 = n448 | n449;
assign n451 = n232 | n367;
assign n452 = n305 | n422 | n533;
assign n453 = n342 | n223;
assign n454 = i_6_ | n229;
assign n455 = n451 & n452 & (n453 | n454);
assign n456 = n636 & n450 & n622 & n579;
assign n457 = n635 & n634 & n633 & n632 & n553 & n552 & ~n432 & n433;
assign n458 = n601 & n249 & n617;
assign n459 = n294 & n297 & n701 & n721 & n206 & n199 & n722 & n155;
assign n460 = ~n252 & ~n529;
assign n461 = i_2_ & ~n426;
assign n462 = n461 & ((~n194 & ~n314) | n460);
assign n463 = n305 | n339;
assign n464 = n463 | n415;
assign n465 = n182 | n534;
assign n466 = n314 | n365;
assign n467 = n241 | n158;
assign n468 = n465 & n466 & (n236 | n467);
assign n469 = i_3_ & i_2_;
assign n470 = n469 & ((~n229 & ~n252) | ~n389);
assign n471 = ~n470 & (i_2_ | n306 | n440);
assign n472 = ~i_6_ | n527;
assign n473 = (n229 | n472) & (i_7_ | n370);
assign n474 = i_3_ | n426;
assign n475 = (n321 | n158) & (i_4_ | n474);
assign n476 = n639 & n638 & n637 & n464 & n148 & ~n462;
assign n477 = n550 & n551 & n552;
assign n478 = n291 & n322 & n324;
assign n479 = n732 & n734 & (~i_1_ | n471);
assign n480 = n554 & n701 & n731 & n730 & n396 & n161 & n688 & n727;
assign n481 = n468 & n420 & n476 & n96 & n477 & n478 & n479 & n480;
assign n482 = n440 | n540;
assign n483 = n482 & (n198 | n415);
assign n484 = n302 | n158;
assign n485 = n166 | n236;
assign n486 = n484 & n485 & (~i_5_ | n440);
assign n487 = i_4_ | ~i_5_;
assign n488 = i_3_ | ~i_0_ | i_2_;
assign n489 = (n487 | n488) & (n373 | n170);
assign n490 = n262 & n92 & n612 & n738 & n739 & n737;
assign n491 = n621 & n649 & n644 & n643 & n289 & n162 & n393 & n736;
assign n492 = n483 & n447 & n481 & n114 & n103 & n442 & n490 & n491;
assign n493 = n241 | n314;
assign n494 = n493 | n422;
assign n495 = n209 | n182;
assign n496 = n425 | n493;
assign n497 = n356 | n182 | n346;
assign n498 = ~n170 & ~n449 & (~n430 | n461);
assign n499 = n332 & (~n378 | ~n485 | ~n740);
assign n500 = n545 | n145 | ~n332;
assign n501 = n531 | n557;
assign n502 = (n342 | n171) & (n449 | n335);
assign n503 = n500 & n501 & n502;
assign n504 = n166 | n274;
assign n505 = n158 | n566;
assign n506 = n422 | n576;
assign n507 = n719 & (n190 | n354 | n561);
assign n508 = n430 | n345;
assign n509 = n476 & n455 & n503 & n293 & n570 & n424;
assign n510 = n611 & n383 & n203 & n213 & n682 & n361;
assign n511 = n317 & n176 & n175 & n643 & n641 & n318;
assign n512 = n166 | n531;
assign n513 = n270 & (n425 | n512);
assign n514 = i_3_ | n530;
assign n515 = i_6_ | n543;
assign n516 = n514 | n515;
assign n517 = n145 | n575;
assign n518 = n166 | n233;
assign n519 = n170 | n566;
assign n520 = n669 & n387 & n217 & n693 & n200;
assign n521 = n404 & n692 & n359 & n744 & n650 & n642 & n483 & n105;
assign n522 = ~n232 & (~n544 | ~n591);
assign n523 = n390 & n104 & n113 & n93 & n141 & n304;
assign n524 = n745 & n746 & n747 & n77 & n381 & n605;
assign n525 = n689 & n271 & n705 & n360 & n47 & n618;
assign n526 = n481 & n435 & n131 & n513 & n503 & n523 & n524 & n525;
assign n527 = i_3_ | ~i_4_;
assign n528 = n305 | n342;
assign n529 = i_7_ | ~i_8_;
assign n530 = i_1_ | i_0_;
assign n531 = ~i_2_ | n530;
assign n532 = n342 | n531;
assign n533 = ~i_3_ | ~i_4_;
assign n534 = n170 | n241;
assign n535 = i_0_ | n443 | n225;
assign n536 = n339 | n430;
assign n537 = n223 | n229;
assign n538 = n531 | n170;
assign n539 = n305 | n158;
assign n540 = n305 | n314;
assign n541 = n422 | n430;
assign n542 = n208 | ~n461;
assign n543 = i_4_ | i_5_;
assign n544 = n415 | n430;
assign n545 = i_4_ | n306;
assign n546 = n305 | n545;
assign n547 = ~i_3_ | ~i_5_;
assign n548 = n430 | n370;
assign n549 = n223 | n158;
assign n550 = n232 | n341;
assign n551 = n170 | n372;
assign n552 = n208 | n540;
assign n553 = n182 | n549;
assign n554 = n208 | n463;
assign n555 = n540 | n454;
assign n556 = n425 | n467;
assign n557 = n422 | n339;
assign n558 = n531 | n314;
assign n559 = ~n332 | n454;
assign n560 = ~i_6_ | i_7_;
assign n561 = i_1_ | n443;
assign n562 = n426 | ~i_3_ | n252;
assign n563 = n236 | n211;
assign n564 = n305 | n232;
assign n565 = n529 | n474;
assign n566 = n422 | ~n461;
assign n567 = n236 | n463;
assign n568 = n536 | n560;
assign n569 = n339 | n341;
assign n570 = n567 & n196 & n568 & n569;
assign n571 = n223 | n314;
assign n572 = n241 | n339;
assign n573 = ~n332 | n415;
assign n574 = i_6_ | i_8_;
assign n575 = ~n461 | n545;
assign n576 = n232 | n531;
assign n577 = i_3_ | n190 | n444;
assign n578 = n49 & n394 & n421 & n387 & n445;
assign n579 = n440 | n564;
assign n580 = n246 & n578 & n243 & n410 & n579 & n418;
assign n581 = ~n461 | n485;
assign n582 = n227 & n230 & n451 & n581;
assign n583 = n422 | n441;
assign n584 = n422 | n571;
assign n585 = n182 | n546;
assign n586 = n425 | n416;
assign n587 = n182 | n436;
assign n588 = n672 & n673 & n606 & n674;
assign n589 = n668 & n626 & n669 & n670 & n671 & n287 & n645 & n296;
assign n590 = ~n332 | n440;
assign n591 = n182 | n531;
assign n592 = n407 & n135 & n692 & n392 & n137 & n693 & n694 & n55;
assign n593 = n695 & n696 & n685 & n687 & n585 & n697 & n698 & n681;
assign n594 = n339 | n559;
assign n595 = n181 | n425;
assign n596 = n418 & n393 & n594 & n595 & n550;
assign n597 = ~n332 | n557;
assign n598 = n425 | n144;
assign n599 = n440 | n571;
assign n600 = n314 | n541;
assign n601 = n600 & n599 & n598 & n597 & n518 & ~n273 & n275;
assign n602 = n182 | n493;
assign n603 = n232 | n274;
assign n604 = n422 | n558;
assign n605 = n170 | n236 | ~n461;
assign n606 = n430 | n485;
assign n607 = n208 | n416;
assign n608 = n551 & n686 & n639 & n637 & n671 & n569 & n57 & n653;
assign n609 = n339 | n159;
assign n610 = n422 | n237;
assign n611 = n237 | n454;
assign n612 = n609 & n395 & n316 & n610 & n611 & n391;
assign n613 = n236 | n416;
assign n614 = n539 | n242;
assign n615 = n181 | n302;
assign n616 = n454 | n564;
assign n617 = n615 & n256 & n269 & n234 & n214 & n270 & n50 & n616;
assign n618 = n529 | n535;
assign n619 = n223 | n557;
assign n620 = n532 | n208;
assign n621 = n422 | n538;
assign n622 = n182 | n571;
assign n623 = n181 | n440;
assign n624 = n182 | n463;
assign n625 = n182 | n195;
assign n626 = n565 | n191;
assign n627 = n397 & n338 & n336 & ~n334 & n82 & ~n333;
assign n628 = n425 | n571;
assign n629 = n342 | n274;
assign n630 = n236 | n342 | ~n461;
assign n631 = n534 | n415;
assign n632 = n232 | n171;
assign n633 = n236 | n539;
assign n634 = n342 | n233;
assign n635 = n672 & (n252 | ~n332 | n529);
assign n636 = n546 | n454;
assign n637 = n232 | n159;
assign n638 = n182 | n416;
assign n639 = n430 | n557;
assign n640 = n422 | n540;
assign n641 = i_2_ | n530;
assign n642 = n402 & n623 & n641 & n394;
assign n643 = n425 | n237;
assign n644 = n237 | n208;
assign n645 = n415 | n564;
assign n646 = n415 | n576;
assign n647 = n138 & n263 & n694 & n610 & n501 & n677 & n297;
assign n648 = n440 | n576;
assign n649 = n440 | n303;
assign n650 = n59 & n57 & n648 & n649 & n587;
assign n651 = n339 | n591;
assign n652 = i_5_ | n236 | n514;
assign n653 = n528 | n422;
assign n654 = n303 | n194;
assign n655 = n742 & n55 & n180;
assign n656 = n181 | n454;
assign n657 = n236 | n448;
assign n658 = n198 | n182;
assign n659 = n214 & n235 & n671 & n58 & n652 & n137;
assign n660 = n528 | n425;
assign n661 = n440 | n572;
assign n662 = n725 & n632 & n581 & n231 & n400 & n699 & n584;
assign n663 = n147 & n143 & n644 & n410 & n296 & n201 & n362 & n743;
assign n664 = n651 & n445 & n628;
assign n665 = n670 & n713 & n668 & n633 & n598 & n600;
assign n666 = n180 & n257 & n151 & n49 & n694 & n742;
assign n667 = n403 & n219 & n555 & n392 & n371 & n629;
assign n668 = n415 | n448;
assign n669 = n208 | n549;
assign n670 = n454 | n441;
assign n671 = n440 | n467;
assign n672 = n440 | n195;
assign n673 = n422 | n209;
assign n674 = n236 | n453;
assign n675 = n198 | n425;
assign n676 = n236 | n493;
assign n677 = n440 | n538;
assign n678 = n301 | n561 | n444;
assign n679 = n208 | n303;
assign n680 = n263 & n610 & n56;
assign n681 = n208 | n467;
assign n682 = n539 | n449;
assign n683 = ~n461 | ~i_3_ | n454;
assign n684 = n658 & n288 & n623 & n653 & n631 & n630 & n595;
assign n685 = n301 | n423;
assign n686 = n301 | n535;
assign n687 = n536 | n229;
assign n688 = n208 | n575;
assign n689 = n422 | n531 | n356;
assign n690 = n241 | n378;
assign n691 = n301 | n241 | n472;
assign n692 = n538 | n454;
assign n693 = n314 | n544;
assign n694 = n440 | n539;
assign n695 = n190 | n548;
assign n696 = n192 | n389;
assign n697 = n208 | n448;
assign n698 = n236 | n335;
assign n699 = n342 | n590;
assign n700 = n153 & (n440 | n223 | n306);
assign n701 = n440 | n549;
assign n702 = n305 | ~i_7_ | n244;
assign n703 = n527 | n182 | n373;
assign n704 = n638 & n235 & n136 & n677 & n669 & n567 & n217;
assign n705 = n540 | n574;
assign n706 = n425 | n241 | n547;
assign n707 = n164 & (n321 | n415 | n543);
assign n708 = n181 | n301;
assign n709 = n674 & (~i_7_ | n223 | n248);
assign n710 = n342 | n541;
assign n711 = n158 | n337;
assign n712 = ~i_3_ | i_5_ | n305 | n415;
assign n713 = n422 | n198;
assign n714 = n712 & (n354 | ~n461 | n529);
assign n715 = n171 | n323;
assign n716 = i_7_ | n244 | ~n461;
assign n717 = n301 | n225 | n226;
assign n718 = n717 & (n419 | n346);
assign n719 = n182 | n453;
assign n720 = n529 | n225 | n488;
assign n721 = n679 & (n226 | n438);
assign n722 = (n449 | n195) & (n223 | n224);
assign n723 = (n527 | n194) & (n301 | n232);
assign n724 = (n529 | n444) & (n190 | n166);
assign n725 = n339 | n233;
assign n726 = n549 | n194;
assign n727 = n517 & n149 & n725 & n726;
assign n728 = i_8_ | n252 | n488;
assign n729 = n728 & (n240 | n373 | n415);
assign n730 = n729 & (i_3_ | n454 | ~n461);
assign n731 = n533 | n236 | ~n332;
assign n732 = (n475 | n425) & (n473 | n241);
assign n733 = (n194 | n512) & (n529 | n540);
assign n734 = n733 & (n430 | (n724 & n723));
assign n735 = ~i_0_ | ~i_2_ | ~i_7_ | n342;
assign n736 = n280 & n89 & n735 & n380 & n169 & n83;
assign n737 = (~n332 | n486) & (n232 | n591);
assign n738 = n489 | n190;
assign n739 = n373 | n208 | n547;
assign n740 = (n533 | n415) & (n422 | n232);
assign n741 = n383 & n295 & n675;
assign n742 = i_4_ | i_6_ | n514;
assign n743 = n215 & n204 & n690 & n162 & n726 & n258;
assign n744 = n184 & (n534 | n236);
assign n745 = ~i_2_ | ~i_5_ | n748 | n749;
assign n746 = i_3_ | n430 | n574;
assign n747 = n487 | n565;
assign n748 = i_1_ & (i_4_ | n229);
assign n749 = ~i_1_ & (~i_4_ | n208);
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:22 2019
module ex1010 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869;
assign o_0_ = ~n418;
assign o_1_ = ~n31;
assign o_2_ = ~n403;
assign o_3_ = ~n378;
assign o_4_ = ~n349;
assign o_5_ = ~n30;
assign o_6_ = ~n270;
assign o_7_ = ~n216;
assign o_8_ = ~n170;
assign o_9_ = ~n109;
assign n30 = n155 & n50 & n301 & n302 & n303 & n304 & n305 & n306;
assign n31 = n97 & n404 & n151 & n405 & n406 & n407 & n408 & n409;
assign n32 = (n436 | n458) & (n219 | n479);
assign n33 = ~i_9_ | n429;
assign n34 = n423 | n446;
assign n35 = n32 & (n33 | n34);
assign n36 = (n222 | n481) & (n43 | n480);
assign n37 = ~i_9_ | n419;
assign n38 = n423 | n457;
assign n39 = n36 & (n37 | n38);
assign n40 = i_9_ | n440;
assign n41 = n420 | n441;
assign n42 = n419 | n450;
assign n43 = i_9_ | n421;
assign n44 = (n42 | n43) & (n40 | n41);
assign n45 = n219 | n103;
assign n46 = n439 | n290;
assign n47 = n565 & n320 & n566;
assign n48 = n563 & n564 & (n272 | n476);
assign n49 = n561 & n562 & n125 & n556 & n560 & n557;
assign n50 = n45 & n46 & n44 & n35 & n39 & n47 & n48 & n49;
assign n51 = n40 | n456;
assign n52 = n436 | n203;
assign n53 = ~i_9_ | n427;
assign n54 = n426 | n446;
assign n55 = n51 & n52 & (n53 | n54);
assign n56 = n37 | n262;
assign n57 = n272 | n487;
assign n58 = n319 & (n219 | n488);
assign n59 = n555 & n55 & (n91 | n489);
assign n60 = n53 | n92;
assign n61 = n219 | n485;
assign n62 = n33 | n486;
assign n63 = n388 & n554 & (n53 | n483);
assign n64 = n56 & n57 & n58 & n59 & n60 & n61 & n62 & n63;
assign n65 = n552 & (n37 | n490);
assign n66 = n436 | n491;
assign n67 = (n33 | n469) & (n96 | n43);
assign n68 = n219 | n339;
assign n69 = (n37 | n478) & (n439 | n494);
assign n70 = n553 & n328 & (n309 | n481);
assign n71 = n65 & n66 & n67 & n68 & n69 & n70;
assign n72 = n91 | n496;
assign n73 = n100 | n41;
assign n74 = (n309 | n463) & (n222 | n495);
assign n75 = (n222 | n463) & (n43 | n255);
assign n76 = (n422 | n462) & (n43 | n223);
assign n77 = n72 & n73 & n74 & n75 & n76;
assign n78 = n219 | n498;
assign n79 = n436 | n480;
assign n80 = (n436 | n447) & (n222 | n497);
assign n81 = (n86 | n475) & (n258 | n499);
assign n82 = (n309 | n480) & (n40 | n493);
assign n83 = n78 & n79 & n80 & n81 & n82;
assign n84 = (n443 | n86) & (n462 | n502);
assign n85 = n225 & n551 & (n258 | n500);
assign n86 = i_9_ | n460;
assign n87 = n433 | n466;
assign n88 = n84 & n85 & (n86 | n87);
assign n89 = (n222 | n203) & (n33 | n150);
assign n90 = n549 & n550 & (n219 | n199);
assign n91 = ~i_9_ | n466;
assign n92 = n435 | n442;
assign n93 = n89 & n90 & (n91 | n92);
assign n94 = n462 | n507;
assign n95 = n548 & n124 & (n100 | n506);
assign n96 = n441 | n442;
assign n97 = n94 & n95 & (n96 | n86);
assign n98 = (n219 | n92) & (n53 | n469);
assign n99 = n431 | n432;
assign n100 = i_9_ | n457;
assign n101 = n98 & (n99 | n100);
assign n102 = (n100 | n508) & (n33 | n489);
assign n103 = n423 | n460;
assign n104 = n102 & (n37 | n103);
assign n105 = (n86 | n465) & (n464 | n219);
assign n106 = n64 & n71 & n50 & n83 & n88 & n77;
assign n107 = n589 & n593 & n592 & n586 & n585 & n588;
assign n108 = n580 & n584 & n583 & n579 & n577 & n575;
assign n109 = n97 & n101 & n93 & n105 & n104 & n106 & n107 & n108;
assign n110 = n623 & (n100 | n514);
assign n111 = n37 | n507;
assign n112 = n86 | (n468 & n492);
assign n113 = n622 & (n462 | n498);
assign n114 = n620 & n621 & (n43 | n310);
assign n115 = n619 & n285 & n561 & n209 & n56 & n618 & n299 & n616;
assign n116 = n110 & n111 & n112 & n113 & n114 & n115;
assign n117 = (n37 | n471) & (n33 | n520);
assign n118 = n53 | n34;
assign n119 = (n91 | n523) & (n462 | n488);
assign n120 = n609 & n608 & (n100 | n475);
assign n121 = n312 & n613 & (n309 | n458);
assign n122 = n611 & n610 & (n447 | n43);
assign n123 = n117 & n118 & n119 & n120 & n121 & n122;
assign n124 = n462 | n505;
assign n125 = n43 | n468;
assign n126 = n73 & (n222 | n518);
assign n127 = (n86 | n525) & (n272 | n465);
assign n128 = n606 & (n309 | n524);
assign n129 = n603 & (n462 | n526);
assign n130 = n601 & n602 & (n439 | n498);
assign n131 = n605 & n604 & (n37 | n461);
assign n132 = n124 & n125 & n126 & n127 & n128 & n129 & n130 & n131;
assign n133 = (n272 | n495) & (n91 | n103);
assign n134 = n454 | n100;
assign n135 = n600 & (n309 | n484);
assign n136 = n462 | n477;
assign n137 = n598 & n599 & (n219 | n500);
assign n138 = n596 & n597 & (n222 | n42);
assign n139 = n133 & n134 & n135 & n136 & n137 & n138;
assign n140 = (n91 | n511) & (n272 | n528);
assign n141 = n594 & n595 & (n91 | n34);
assign n142 = n420 | n432;
assign n143 = n140 & n141 & (n86 | n142);
assign n144 = (n272 | n529) & (n258 | n503);
assign n145 = n86 | n530;
assign n146 = (n53 | n103) & (n424 | n462);
assign n147 = n144 & n145 & n146 & n61;
assign n148 = (n309 | n531) & (n436 | n456);
assign n149 = (n86 | n532) & (n100 | n472);
assign n150 = n421 | n442;
assign n151 = n148 & n149 & (n91 | n150);
assign n152 = (n40 & n436) | n533;
assign n153 = n380 & (n53 | n496);
assign n154 = n423 | n435;
assign n155 = n152 & n153 & (n91 | n154);
assign n156 = (n100 | n531) & (n91 | n534);
assign n157 = n426 | n466;
assign n158 = n156 & (n86 | n157);
assign n159 = (n33 | n505) & (n91 | n38);
assign n160 = n433 | n460;
assign n161 = n159 & (n33 | n160);
assign n162 = (n436 | n513) & (n33 | n92);
assign n163 = (n53 | n509) & (n222 | n512);
assign n164 = (n222 | n513) & (n37 | n467);
assign n165 = (n258 | n467) & (n43 | n501);
assign n166 = n626 & n625 & (n309 | n42);
assign n167 = n633 & n634 & n631 & n630 & n629 & n387 & n628 & n627;
assign n168 = n139 & n143 & n147 & n151 & n123 & n132 & n116 & n644;
assign n169 = n640 & n641 & n639 & n638 & n637 & n642 & n636 & n635;
assign n170 = n162 & n163 & n164 & n165 & n166 & n167 & n168 & n169;
assign n171 = (n37 | n92) & (n43 | n484);
assign n172 = n648 & n649 & (n458 | n86);
assign n173 = n647 & (n100 | n294);
assign n174 = n645 & n646 & (n219 | n540);
assign n175 = n171 & n172 & n173 & n174;
assign n176 = n33 | n477;
assign n177 = n272 | n255;
assign n178 = (n91 | n538) & (n452 | n43);
assign n179 = n91 | n504;
assign n180 = (n100 | n492) & (n258 | n504);
assign n181 = n559 & (n53 | n290);
assign n182 = n176 & n177 & n178 & n179 & n180 & n181;
assign n183 = n428 | n100;
assign n184 = n219 | n34;
assign n185 = (n436 | n472) & (n43 | n474);
assign n186 = n40 | n542;
assign n187 = (n91 | n339) & (n445 | n219);
assign n188 = (n40 | n525) & (n219 | n505);
assign n189 = n183 & n184 & n185 & n186 & n187 & n188;
assign n190 = n436 | n525;
assign n191 = n86 | n512;
assign n192 = (n86 | n480) & (n436 | n544);
assign n193 = n53 | n486;
assign n194 = n309 | n543;
assign n195 = (n258 | n251) & (n222 | n294);
assign n196 = n190 & n191 & n192 & n193 & n194 & n195;
assign n197 = (n96 | n100) & (n272 | n532);
assign n198 = n350 & n351 & (n40 | n513);
assign n199 = n450 | n457;
assign n200 = n197 & n198 & (n53 | n199);
assign n201 = (n462 | n496) & (n37 | n522);
assign n202 = (n309 | n517) & (n439 | n539);
assign n203 = n423 | n432;
assign n204 = n201 & n202 & (n86 | n203);
assign n205 = (n222 | n142) & (n272 | n521);
assign n206 = (n439 | n496) & (n33 | n470);
assign n207 = n205 & n206;
assign n208 = (n86 | n519) & (n100 | n537);
assign n209 = n53 | n150;
assign n210 = n674 & n673 & (n272 | n514);
assign n211 = n566 & n563 & n234 & n605 & n672 & n671;
assign n212 = n64 & n139 & (n461 | n91);
assign n213 = n676 & n675 & (n53 | n539);
assign n214 = n196 & n200 & n204 & n207 & n182 & n189 & n175;
assign n215 = n670 & n227 & n668 & n667 & n663 & n662 & n666 & n661;
assign n216 = n208 & n209 & n210 & n211 & n212 & n213 & n214 & n215;
assign n217 = n258 | n92;
assign n218 = (n309 | n542) & (n40 | n518);
assign n219 = ~i_9_ | n451;
assign n220 = n217 & n218 & (n219 | n38);
assign n221 = (n86 | n513) & (n462 | n545);
assign n222 = i_9_ | n425;
assign n223 = n442 | n466;
assign n224 = n221 & (n222 | n223);
assign n225 = n272 | n501;
assign n226 = n438 | n439;
assign n227 = n456 | n100;
assign n228 = n45 & n72 & (n43 | n525);
assign n229 = n686 & n685 & (n309 | n294);
assign n230 = n276 & n652 & n684 & n277;
assign n231 = n224 & n158 & n220 & n44 & n404 & n693 & n692 & n690;
assign n232 = n225 & n226 & n227 & n176 & n228 & n229 & n230 & n231;
assign n233 = n434 | n33;
assign n234 = n462 | n478;
assign n235 = n674 & (n40 | n536);
assign n236 = (n258 | n527) & (n222 | n510);
assign n237 = n33 | n523;
assign n238 = (n40 | n519) & (n37 | n259);
assign n239 = n439 | (n339 & n516);
assign n240 = n682 & n683 & (n100 | n541);
assign n241 = n233 & n234 & n235 & n236 & n237 & n238 & n239 & n240;
assign n242 = (n53 | n534) & (n462 | n54);
assign n243 = n96 | n272;
assign n244 = n681 & (n86 | n501);
assign n245 = n43 | n491;
assign n246 = n46 & n615 & (n91 | n479);
assign n247 = n679 & n680 & (n436 | n508);
assign n248 = n242 & n243 & n244 & n245 & n246 & n247;
assign n249 = n392 & (n40 | n492);
assign n250 = n678 & n677 & (n33 | n546);
assign n251 = n442 | n446;
assign n252 = n249 & n250 & (n53 | n251);
assign n253 = n272 | n536;
assign n254 = (n258 | n540) & (n86 | n515);
assign n255 = n431 | n441;
assign n256 = n253 & n254 & (n40 | n255);
assign n257 = (n91 | n520) & (n456 | n43);
assign n258 = ~i_9_ | n441;
assign n259 = n420 | n440;
assign n260 = n257 & (n258 | n259);
assign n261 = (n222 | n468) & (n258 | n339);
assign n262 = n420 | n449;
assign n263 = n261 & (n53 | n262);
assign n264 = (n37 | n290) & (n454 | n86);
assign n265 = (n219 | n511) & (n33 | n494);
assign n266 = n710 & n709 & (n309 | n506);
assign n267 = n713 & n712 & (n33 | n479);
assign n268 = n252 & n256 & n260 & n263 & n241 & n248 & n232 & n717;
assign n269 = n700 & n177 & n699 & n698 & n695 & n694 & n697 & n708;
assign n270 = n264 & n265 & n266 & n267 & n268 & n269;
assign n271 = (n100 | n535) & (n439 | n251);
assign n272 = i_9_ | n449;
assign n273 = n271 & (n272 | n42);
assign n274 = n91 | n546;
assign n275 = n439 | n546;
assign n276 = n436 | n476;
assign n277 = n219 | n150;
assign n278 = n253 & n719 & (n309 | n528);
assign n279 = n714 & (n91 | n526);
assign n280 = n321 & (n37 | n438);
assign n281 = n721 & n720 & (n86 | n41);
assign n282 = n274 & n275 & n276 & n277 & n278 & n279 & n280 & n281;
assign n283 = n219 | n478;
assign n284 = n428 | n436;
assign n285 = n100 | n521;
assign n286 = n665 & (n455 | n219);
assign n287 = n161 & n283 & n263 & n284 & n285 & n286;
assign n288 = (n40 | n497) & (n37 | n539);
assign n289 = n718 & (n219 | n486);
assign n290 = n453 | n460;
assign n291 = n288 & n289 & (n290 | n91);
assign n292 = n43 | (n476 & n506);
assign n293 = n686 & (n53 | n473);
assign n294 = n423 | n466;
assign n295 = n292 & n293 & (n272 | n294);
assign n296 = n219 | n469;
assign n297 = n100 | n533;
assign n298 = (n272 | n543) & (n462 | n486);
assign n299 = n455 | n53;
assign n300 = n296 & n297 & n298 & n299;
assign n301 = (n436 | n529) & (n219 | n547);
assign n302 = n749 & n748 & (n91 | n516);
assign n303 = n282 & n287 & n291 & n295 & n300 & n252 & n224 & n196;
assign n304 = n747 & n746 & n745 & n744 & n743 & n742 & n741 & n740;
assign n305 = n738 & n739 & n730 & n732 & n731 & n737 & n736 & n735;
assign n306 = n729 & n728 & n727 & n726 & n725 & n724 & n723 & n722;
assign n307 = n678 & (n219 | n490);
assign n308 = (n219 | n507) & (n459 | n462);
assign n309 = i_9_ | n446;
assign n310 = n419 | n433;
assign n311 = n307 & n308 & (n309 | n310);
assign n312 = n53 | n503;
assign n313 = n710 & n632 & (n309 | n501);
assign n314 = n753 & n590 & n190 & n78 & n79 & n51;
assign n315 = n469 | n91;
assign n316 = n669 & n649 & (n37 | n477);
assign n317 = n751 & n752 & (n439 | n92);
assign n318 = n311 & n312 & n313 & n314 & n315 & n234 & n316 & n317;
assign n319 = n447 | n100;
assign n320 = n219 | n477;
assign n321 = n219 | n154;
assign n322 = (n439 | n461) & (n100 | n530);
assign n323 = n222 | n472;
assign n324 = n654 & (n91 | n259);
assign n325 = (n222 | n537) & (n37 | n482);
assign n326 = n750 & n738 & (n272 | n484);
assign n327 = n319 & n320 & n321 & n322 & n323 & n324 & n325 & n326;
assign n328 = n436 | n492;
assign n329 = n53 | n489;
assign n330 = n452 | n100;
assign n331 = (n465 | n43) & (n272 | n512);
assign n332 = (n439 | n538) & (n37 | n527);
assign n333 = n462 | n538;
assign n334 = (n462 | n520) & (n424 | n219);
assign n335 = n258 | n490;
assign n336 = n328 & n329 & n330 & n331 & n332 & n333 & n334 & n335;
assign n337 = n53 | n520;
assign n338 = n43 | n203;
assign n339 = n420 | n425;
assign n340 = n337 & n338 & (n53 | n339);
assign n341 = n759 & n758 & (n462 | n527);
assign n342 = n602 & n757 & (n258 | n479);
assign n343 = n614 & n756 & (n43 | n497);
assign n344 = n755 & n754 & (n43 | n294);
assign n345 = n599 & n274 & n761 & n763 & n762 & n765 & n764 & n766;
assign n346 = n773 & n621 & n772 & n771;
assign n347 = n769 & n770 & n552 & n562 & n768 & n767;
assign n348 = n340 & n300 & n248 & n220 & n327 & n336 & n318 & n777;
assign n349 = n341 & n342 & n343 & n344 & n345 & n346 & n347 & n348;
assign n350 = n99 | n272;
assign n351 = n462 | n103;
assign n352 = n340 & (n459 | n219);
assign n353 = (n436 | n468) & (n33 | n467);
assign n354 = n94 & n582 & (n43 | n541);
assign n355 = n315 & n782 & (n258 | n511);
assign n356 = n739 & n780 & (n222 | n491);
assign n357 = n297 & n350 & n351 & n352 & n353 & n354 & n355 & n356;
assign n358 = (n436 | n532) & (n91 | n470);
assign n359 = n40 | n528;
assign n360 = (n43 | n515) & (n424 | n53);
assign n361 = n222 | n536;
assign n362 = n779 & n676 & (n100 | n142);
assign n363 = n778 & n760 & (n91 | n477);
assign n364 = n358 & n359 & n360 & n361 & n362 & n363;
assign n365 = (n222 | n524) & (n436 | n537);
assign n366 = n100 | n532;
assign n367 = (n91 | n498) & (n40 | n541);
assign n368 = (n33 | n154) & (n222 | n541);
assign n369 = n53 | n502;
assign n370 = n569 & (n436 | n157);
assign n371 = n365 & n366 & n367 & n368 & n369 & n370;
assign n372 = n801 & n800 & (n455 | n462);
assign n373 = n798 & n797 & (n272 | n530);
assign n374 = n364 & n371 & n357 & n804 & n88 & n55 & n116 & n803;
assign n375 = n795 & n794 & (n290 | n219);
assign n376 = n792 & n791 & (n100 | n493);
assign n377 = n788 & n789 & n787 & n786 & n785 & n217 & n784 & n783;
assign n378 = n372 & n373 & n374 & n375 & n376 & n377;
assign n379 = n462 | (n444 & n534);
assign n380 = n258 | n507;
assign n381 = n808 & (n53 | n471);
assign n382 = n809 & n810 & (n100 | n501);
assign n383 = n806 & n807 & (n53 | n461);
assign n384 = n759 & n805 & (n40 | n484);
assign n385 = n379 & n380 & n381 & n382 & n383 & n384;
assign n386 = n86 | n514;
assign n387 = n219 | n496;
assign n388 = n91 | n482;
assign n389 = n101 & (n272 | n519);
assign n390 = n40 | n514;
assign n391 = n37 | n154;
assign n392 = n430 | n100;
assign n393 = n596 & n597 & (n439 | n520);
assign n394 = n386 & n387 & n388 & n389 & n390 & n391 & n392 & n393;
assign n395 = (n222 | n447) & (n37 | n339);
assign n396 = n43 | (n454 & n510);
assign n397 = n811 & (n37 | n434);
assign n398 = n813 & (n462 | n546);
assign n399 = n812 & (n53 | n498);
assign n400 = n817 & n818 & (n439 | n103);
assign n401 = n816 & n815 & (n272 | n508);
assign n402 = n182 & n143 & n260 & n827 & n93 & n828 & n826 & n822;
assign n403 = n395 & n396 & n397 & n398 & n399 & n400 & n401 & n402;
assign n404 = n33 | n534;
assign n405 = (n37 | n502) & (n86 | n524);
assign n406 = (n100 | n518) & (n222 | n454);
assign n407 = n318 & n287 & n256 & n200 & n394 & n364 & n273;
assign n408 = n111 & n606 & n808 & n849 & n848 & n847 & n846 & n845;
assign n409 = n843 & n564 & n842 & n840 & n832 & n831 & n830 & n836;
assign n410 = (n86 | n533) & (n439 | n199);
assign n411 = n438 | n91;
assign n412 = n858 & n555 & (n43 | n533);
assign n413 = n721 & n857 & (n100 | n517);
assign n414 = n781 & n856 & (n462 | n499);
assign n415 = n855 & n854 & (n309 | n468);
assign n416 = n852 & n851 & (n33 | n444);
assign n417 = n132 & n83 & n175 & n868 & n867 & n869 & n866 & n862;
assign n418 = n410 & n411 & n412 & n413 & n414 & n415 & n416 & n417;
assign n419 = i_8_ | i_6_ | ~i_7_;
assign n420 = ~i_5_ | ~i_3_ | i_4_;
assign n421 = ~i_0_ | ~i_1_ | ~i_2_;
assign n422 = n420 | n421;
assign n423 = i_5_ | i_3_ | ~i_4_;
assign n424 = n421 | n423;
assign n425 = ~i_0_ | ~i_1_ | i_2_;
assign n426 = ~i_3_ | ~i_4_ | i_5_;
assign n427 = ~i_6_ | ~i_7_ | i_8_;
assign n428 = n426 | n427;
assign n429 = ~i_6_ | ~i_7_ | ~i_8_;
assign n430 = n420 | n429;
assign n431 = ~i_5_ | i_3_ | i_4_;
assign n432 = i_8_ | i_6_ | i_7_;
assign n433 = i_5_ | i_3_ | i_4_;
assign n434 = n425 | n433;
assign n435 = ~i_2_ | ~i_0_ | i_1_;
assign n436 = i_9_ | n435;
assign n437 = i_8_ | ~i_6_ | i_7_;
assign n438 = n433 | n435;
assign n439 = ~i_9_ | n437;
assign n440 = i_2_ | ~i_0_ | i_1_;
assign n441 = ~i_8_ | ~i_6_ | i_7_;
assign n442 = ~i_3_ | ~i_4_ | ~i_5_;
assign n443 = n419 | n442;
assign n444 = n431 | n440;
assign n445 = n433 | n440;
assign n446 = ~i_2_ | i_0_ | ~i_1_;
assign n447 = n419 | n420;
assign n448 = n431 | n437;
assign n449 = i_2_ | i_0_ | ~i_1_;
assign n450 = i_5_ | ~i_3_ | i_4_;
assign n451 = ~i_8_ | i_6_ | ~i_7_;
assign n452 = n450 | n451;
assign n453 = ~i_5_ | i_3_ | ~i_4_;
assign n454 = n429 | n453;
assign n455 = n423 | n449;
assign n456 = n423 | n441;
assign n457 = ~i_2_ | i_0_ | i_1_;
assign n458 = n429 | n431;
assign n459 = n433 | n457;
assign n460 = i_2_ | i_0_ | i_1_;
assign n461 = n450 | n460;
assign n462 = ~i_9_ | n432;
assign n463 = n423 | n429;
assign n464 = n431 | n460;
assign n465 = n427 | n433;
assign n466 = ~i_8_ | i_6_ | i_7_;
assign n467 = n421 | n450;
assign n468 = n423 | n437;
assign n469 = n421 | n431;
assign n470 = n425 | n426;
assign n471 = n425 | n453;
assign n472 = n433 | n441;
assign n473 = n426 | n440;
assign n474 = n453 | n466;
assign n475 = n423 | n451;
assign n476 = n432 | n450;
assign n477 = n426 | n457;
assign n478 = n420 | n460;
assign n479 = n420 | n435;
assign n480 = n432 | n453;
assign n481 = n426 | n429;
assign n482 = n421 | n426;
assign n483 = n421 | n453;
assign n484 = n427 | n453;
assign n485 = n425 | n431;
assign n486 = n431 | n446;
assign n487 = n420 | n427;
assign n488 = n431 | n449;
assign n489 = n453 | n457;
assign n490 = n425 | n450;
assign n491 = n420 | n466;
assign n492 = n429 | n450;
assign n493 = n441 | n453;
assign n494 = n442 | n449;
assign n495 = n429 | n433;
assign n496 = n426 | n460;
assign n497 = n431 | n466;
assign n498 = n431 | n435;
assign n499 = n449 | n453;
assign n500 = n440 | n450;
assign n501 = n442 | n451;
assign n502 = n431 | n457;
assign n503 = n423 | n440;
assign n504 = n426 | n449;
assign n505 = n435 | n453;
assign n506 = n420 | n437;
assign n507 = n442 | n460;
assign n508 = n419 | n423;
assign n509 = n423 | n425;
assign n510 = n437 | n453;
assign n511 = n420 | n457;
assign n512 = n441 | n450;
assign n513 = n419 | n426;
assign n514 = n432 | n433;
assign n515 = n433 | n451;
assign n516 = n435 | n450;
assign n517 = n426 | n451;
assign n518 = n433 | n437;
assign n519 = n451 | n453;
assign n520 = n421 | n433;
assign n521 = n437 | n442;
assign n522 = n426 | n435;
assign n523 = n442 | n457;
assign n524 = n429 | n442;
assign n525 = n427 | n442;
assign n526 = n420 | n446;
assign n527 = n440 | n442;
assign n528 = n431 | n451;
assign n529 = n426 | n441;
assign n530 = n420 | n451;
assign n531 = n437 | n450;
assign n532 = n427 | n431;
assign n533 = n427 | n450;
assign n534 = n433 | n446;
assign n535 = n419 | n453;
assign n536 = n432 | n442;
assign n537 = n423 | n427;
assign n538 = n446 | n453;
assign n539 = n449 | n450;
assign n540 = n433 | n449;
assign n541 = n426 | n432;
assign n542 = n419 | n431;
assign n543 = n426 | n437;
assign n544 = n450 | n466;
assign n545 = n446 | n450;
assign n546 = n440 | n453;
assign n547 = n425 | n442;
assign n548 = n462 | n259;
assign n549 = n439 | n504;
assign n550 = n91 | n503;
assign n551 = (n222 | n493) & (n424 | n33);
assign n552 = n53 | n479;
assign n553 = n436 | n493;
assign n554 = (n222 | n484) & (n33 | n339);
assign n555 = n456 | n86;
assign n556 = n315 & n338 & (n462 | n470);
assign n557 = n323 & n411 & (n33 | n471);
assign n558 = n40 | n157;
assign n559 = n91 | n473;
assign n560 = n558 & n559 & (n309 | n474);
assign n561 = n53 | n467;
assign n562 = n157 | n43;
assign n563 = n309 | n475;
assign n564 = n272 | n203;
assign n565 = n428 | n86;
assign n566 = n33 | n478;
assign n567 = (n219 | n467) & (n422 | n37);
assign n568 = (n37 | n424) & (n91 | n483);
assign n569 = n222 | n430;
assign n570 = n569 & (n428 | n222);
assign n571 = (n222 | n99) & (n258 | n485);
assign n572 = (n436 | n510) & (n434 | n439);
assign n573 = n99 | n436;
assign n574 = n33 | n509;
assign n575 = n572 & n573 & n571 & n233 & n570 & n574 & n568 & n567;
assign n576 = n96 | n40;
assign n577 = n576 & n226 & (n40 | n443);
assign n578 = (n33 | n445) & (n37 | n444);
assign n579 = n578 & (n439 | n54);
assign n580 = n309 | (n447 & n448);
assign n581 = n272 | n454;
assign n582 = n272 | n452;
assign n583 = n581 & n582 & (n272 | n493);
assign n584 = n443 | n272;
assign n585 = (n33 & n258) | n455;
assign n586 = (n33 | n511) & (n272 | n456);
assign n587 = n100 | n42;
assign n588 = n587 & n330 & (n100 | n203);
assign n589 = (n459 | n53) & (n100 | n458);
assign n590 = n463 | n86;
assign n591 = n290 | n462;
assign n592 = n590 & n591 & (n448 | n86);
assign n593 = n258 | n461;
assign n594 = n40 | n476;
assign n595 = n91 | n527;
assign n596 = n458 | n43;
assign n597 = n439 | n505;
assign n598 = n40 | n524;
assign n599 = n40 | n465;
assign n600 = n91 | n262;
assign n601 = n258 | n498;
assign n602 = n436 | n223;
assign n603 = n40 | n521;
assign n604 = (n258 | n477) & (n309 | n510);
assign n605 = n439 | n38;
assign n606 = n430 | n436;
assign n607 = n100 | n481;
assign n608 = n607 & (n100 | n484);
assign n609 = n100 | n463;
assign n610 = n549 & n584 & (n43 | n521);
assign n611 = n422 | n258;
assign n612 = n222 | n456;
assign n613 = n612 & (n439 | n485);
assign n614 = n219 | n520;
assign n615 = n436 | n518;
assign n616 = n614 & n615 & (n219 | n470);
assign n617 = n40 | n508;
assign n618 = n617 & (n219 | n503);
assign n619 = n86 | n472;
assign n620 = n222 | n443;
assign n621 = n462 | n339;
assign n622 = (n436 | n42) & (n439 | n522);
assign n623 = n219 | n259;
assign n624 = n40 | (n491 & n529);
assign n625 = n391 & n624 & (n436 | n514);
assign n626 = (n40 | n458) & (n33 | n500);
assign n627 = (n272 | n497) & (n258 | n262);
assign n628 = (n33 | n38) & (n272 | n87);
assign n629 = (n33 | n502) & (n100 | n468);
assign n630 = (n33 | n461) & (n91 | n478);
assign n631 = (n219 | n482) & (n86 | n294);
assign n632 = n462 | n467;
assign n633 = n632 & (n43 | n495);
assign n634 = n222 | n501;
assign n635 = (n436 | n443) & (n222 | n515);
assign n636 = (n37 | n479) & (n462 | n92);
assign n637 = (n40 | n517) & (n37 | n516);
assign n638 = n309 | (n491 & n497);
assign n639 = (n272 | n518) & (n37 | n499);
assign n640 = (n100 | n519) & (n219 | n489);
assign n641 = n100 | n87;
assign n642 = n91 | n251;
assign n643 = (n258 | n464) & (n86 | n535);
assign n644 = n158 & n161 & n155 & n71 & n35 & n643;
assign n645 = n436 | n454;
assign n646 = n43 | n87;
assign n647 = n272 | n310;
assign n648 = n86 | n541;
assign n649 = n439 | n502;
assign n650 = n43 | (n493 & n513);
assign n651 = (n258 | n520) & (n43 | n475);
assign n652 = n53 | n470;
assign n653 = n652 & (n439 | n470);
assign n654 = n222 | n532;
assign n655 = n654 & (n91 | n509);
assign n656 = (n434 | n91) & (n222 | n528);
assign n657 = (n436 | n536) & (n222 | n87);
assign n658 = n436 | n484;
assign n659 = n658 & (n462 | n516);
assign n660 = n462 | n154;
assign n661 = n659 & n660 & n657 & n656 & n655 & n653 & n651 & n650;
assign n662 = (n40 | n42) & (n436 | n465);
assign n663 = n40 | (n510 & n537);
assign n664 = (n37 | n445) & (n40 | n448);
assign n665 = n258 | n54;
assign n666 = n665 & n664 & (n309 | n536);
assign n667 = (n272 | n517) & (n37 | n34);
assign n668 = (n100 | n529) & (n53 | n523);
assign n669 = n462 | n199;
assign n670 = n669 & (n100 | n513);
assign n671 = (n37 | n503) & (n33 | n527);
assign n672 = (n219 | n538) & (n444 | n91);
assign n673 = (n272 | n524) & (n258 | n34);
assign n674 = n272 | n463;
assign n675 = (n219 | n526) & (n309 | n157);
assign n676 = n439 | n507;
assign n677 = (n439 | n479) & (n258 | n150);
assign n678 = n309 | n537;
assign n679 = n436 | n531;
assign n680 = n430 | n43;
assign n681 = n309 | n530;
assign n682 = n272 | n492;
assign n683 = n309 | n508;
assign n684 = n219 | n483;
assign n685 = (n33 | n545) & (n439 | n473);
assign n686 = n33 | n488;
assign n687 = n43 | n528;
assign n688 = n687 & (n33 | n490);
assign n689 = n53 | n494;
assign n690 = n689 & n688 & (n53 | n527);
assign n691 = n462 | n540;
assign n692 = n691 & n623 & (n272 | n535);
assign n693 = (n219 | n509) & (n37 | n523);
assign n694 = (n462 | n509) & (n43 | n518);
assign n695 = (n40 | n487) & (n53 | n505);
assign n696 = (n444 | n53) & (n40 | n544);
assign n697 = n390 & n696 & (n428 | n309);
assign n698 = (n37 | n538) & (n258 | n545);
assign n699 = n179 & (n91 | n494);
assign n700 = (n439 | n262) & (n272 | n41);
assign n701 = (n91 | n199) & (n258 | n523);
assign n702 = (n258 | n38) & (n100 | n476);
assign n703 = n619 & (n86 | n518);
assign n704 = (n222 | n448) & (n43 | n142);
assign n705 = (n436 | n530) & (n462 | n522);
assign n706 = (n436 | n515) & (n219 | n516);
assign n707 = n706 & (n436 | n310);
assign n708 = n550 & n60 & n703 & n702 & n701 & n705 & n704 & n707;
assign n709 = (n309 | n512) & (n53 | n545);
assign n710 = n40 | n515;
assign n711 = n351 & (n99 | n86);
assign n712 = n620 & n711 & (n43 | n543);
assign n713 = (n272 | n472) & (n91 | n54);
assign n714 = n309 | n535;
assign n715 = n714 & (n430 | n40);
assign n716 = (n219 | n494) & (n33 | n540);
assign n717 = n207 & n123 & n104 & n39 & n716 & n715;
assign n718 = (n40 | n506) & (n258 | n470);
assign n719 = (n272 | n542) & (n53 | n499);
assign n720 = (n436 | n517) & (n43 | n544);
assign n721 = n53 | n477;
assign n722 = (n53 | n482) & (n439 | n150);
assign n723 = (n439 | n483) & (n422 | n219);
assign n724 = (n43 | n508) & (n424 | n258);
assign n725 = (n33 & n258) | n547;
assign n726 = n222 | (n487 & n543);
assign n727 = (n33 | n516) & (n439 | n490);
assign n728 = n598 & (n436 | n528);
assign n729 = n595 & (n462 | n500);
assign n730 = (n40 | n535) & (n37 | n546);
assign n731 = n186 & (n309 | n142);
assign n732 = n309 | (n255 & n519);
assign n733 = (n430 | n272) & (n309 | n514);
assign n734 = n100 | n524;
assign n735 = n734 & n733 & (n272 | n475);
assign n736 = (n258 | n489) & (n100 | n536);
assign n737 = (n258 | n103) & (n462 | n38);
assign n738 = n444 | n219;
assign n739 = n462 | n503;
assign n740 = n386 & (n258 | n160);
assign n741 = (n422 | n33) & (n43 | n524);
assign n742 = (n222 | n521) & (n448 | n43);
assign n743 = n436 | (n495 & n512);
assign n744 = n681 & (n37 | n494);
assign n745 = (n219 | n523) & (n272 | n541);
assign n746 = (n37 | n496) & (n258 | n199);
assign n747 = n612 & (n434 | n258);
assign n748 = (n219 | n502) & (n272 | n537);
assign n749 = n219 | n522;
assign n750 = n219 | n262;
assign n751 = (n222 | n506) & (n43 | n472);
assign n752 = n595 & n194 & (n436 | n448);
assign n753 = n462 | n471;
assign n754 = (n258 | n483) & (n43 | n531);
assign n755 = n424 | n91;
assign n756 = n222 | (n529 & n530);
assign n757 = (n434 | n219) & (n222 | n542);
assign n758 = (n37 | n498) & (n436 | n294);
assign n759 = n258 | n546;
assign n760 = n40 | n472;
assign n761 = n760 & (n445 | n258);
assign n762 = (n309 | n525) & (n439 | n445);
assign n763 = (n309 | n493) & (n462 | n251);
assign n764 = n118 & (n219 | n534);
assign n765 = n272 | (n157 & n506);
assign n766 = n600 & n607 & (n33 | n539);
assign n767 = (n86 | n536) & (n37 | n511);
assign n768 = (n219 | n160) & (n86 | n517);
assign n769 = n222 | n519;
assign n770 = n222 | n525;
assign n771 = n40 | (n468 & n543);
assign n772 = (n91 | n486) & (n33 | n526);
assign n773 = n100 | (n495 & n544);
assign n774 = (n436 | n542) & (n222 | n517);
assign n775 = (n439 | n34) & (n40 | n463);
assign n776 = n258 | n534;
assign n777 = n189 & n147 & n77 & n776 & n775 & n774;
assign n778 = n309 | n476;
assign n779 = n436 | n519;
assign n780 = n680 & n652 & (n33 | n483);
assign n781 = n439 | n499;
assign n782 = n781 & n734 & (n37 | n486);
assign n783 = (n422 | n53) & (n43 | n517);
assign n784 = (n222 | n452) & (n258 | n469);
assign n785 = (n222 | n535) & (n462 | n490);
assign n786 = (n436 | n475) & (n91 | n522);
assign n787 = (n438 | n219) & (n33 | n498);
assign n788 = (n219 | n546) & (n37 | n500);
assign n789 = n445 | n91;
assign n790 = (n447 | n272) & (n37 | n504);
assign n791 = n184 & n790 & (n40 | n87);
assign n792 = (n53 & n258) | n488;
assign n793 = (n100 | n310) & (n91 | n502);
assign n794 = n793 & (n86 | n223);
assign n795 = n86 | (n491 & n529);
assign n796 = n558 & (n86 | n537);
assign n797 = n769 & n796 & (n43 | n542);
assign n798 = n753 & (n258 | n516);
assign n799 = (n258 | n526) & (n100 | n512);
assign n800 = n691 & n799 & (n272 | n531);
assign n801 = (n272 | n491) & (n33 | n504);
assign n802 = (n86 | n310) & (n37 | n199);
assign n803 = n44 & n802 & (n439 | n477);
assign n804 = n241 & n204 & n282;
assign n805 = n658 & n755 & (n91 | n500);
assign n806 = (n459 | n91) & (n53 | n504);
assign n807 = n57 & (n219 | n471);
assign n808 = n422 | n439;
assign n809 = n749 & (n222 | n465);
assign n810 = (n428 | n43) & (n462 | n150);
assign n811 = (n37 | n485) & (n222 | n533);
assign n812 = n436 | (n463 & n524);
assign n813 = n40 | (n142 & n530);
assign n814 = (n445 | n462) & (n444 | n258);
assign n815 = n814 & (n443 | n309);
assign n816 = (n272 | n481) & (n309 | n529);
assign n817 = (n258 | n478) & (n53 | n511);
assign n818 = n68 & n62 & (n439 | n160);
assign n819 = (n467 | n91) & (n462 | n482);
assign n820 = n687 & n819 & (n439 | n509);
assign n821 = (n33 | n473) & (n53 | n516);
assign n822 = n821 & n820 & (n40 | n531);
assign n823 = n91 | n499;
assign n824 = n823 & n689 & (n53 | n540);
assign n825 = (n436 | n543) & (n86 | n495);
assign n826 = n825 & n824 & (n258 | n505);
assign n827 = (n42 | n86) & (n428 | n272);
assign n828 = n394 & n357 & n385 & n311 & n295 & n336;
assign n829 = (n43 | n514) & (n462 | n483);
assign n830 = n684 & n829 & (n443 | n43);
assign n831 = (n91 | n490) & (n222 | n41);
assign n832 = (n436 | n501) & (n462 | n485);
assign n833 = (n436 | n41) & (n33 | n522);
assign n834 = n645 & n833 & (n438 | n258);
assign n835 = n603 & (n40 | n474);
assign n836 = n835 & n834 & (n309 | n521);
assign n837 = (n219 | n499) & (n272 | n142);
assign n838 = n683 & n837 & (n462 | n262);
assign n839 = (n272 | n458) & (n455 | n91);
assign n840 = n839 & n838 & (n439 | n488);
assign n841 = n647 & (n100 | n223);
assign n842 = n609 & n841 & (n439 | n511);
assign n843 = n33 | (n459 & n464);
assign n844 = (n436 | n506) & (n53 | n490);
assign n845 = n565 & n844 & (n43 | n41);
assign n846 = (n219 | n251) & (n91 | n505);
assign n847 = n37 | (n54 & n251);
assign n848 = (n439 | n540) & (n430 | n309);
assign n849 = n611 & (n462 | n464);
assign n850 = (n436 | n535) & (n43 | n487);
assign n851 = n275 & n850 & (n40 | n452);
assign n852 = n617 & (n40 | n475);
assign n853 = (n96 | n309) & (n40 | n310);
assign n854 = n853 & (n309 | n492);
assign n855 = (n258 | n538) & (n309 | n544);
assign n856 = (n219 | n504) & (n462 | n494);
assign n857 = n37 | n455;
assign n858 = n43 | n536;
assign n859 = (n37 & n53) | n547;
assign n860 = n779 & n859 & (n222 | n508);
assign n861 = n53 | (n154 & n259);
assign n862 = n861 & n860 & (n40 | n512);
assign n863 = (n53 | n538) & (n439 | n500);
assign n864 = n863 & (n100 | n543);
assign n865 = (n462 | n489) & (n100 | n510);
assign n866 = n865 & n864 & (n448 | n100);
assign n867 = (n436 | n481) & (n462 | n34);
assign n868 = (n436 | n474) & (n258 | n494);
assign n869 = n385 & n371 & n273 & n291 & n232 & n327;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:57 2019
module ex5p (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_;
wire n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300,
n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444,
n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516,
n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597;
assign o_0_ = ~n365;
assign o_1_ = ~n361;
assign o_2_ = ~n403;
assign o_3_ = ~n370;
assign o_4_ = ~n450;
assign o_5_ = ~n357;
assign o_6_ = ~n136;
assign o_7_ = ~n180;
assign o_8_ = ~n452;
assign o_9_ = ~n491;
assign o_10_ = ~n139;
assign o_11_ = ~n179;
assign o_12_ = ~n385;
assign o_13_ = ~n471;
assign o_14_ = ~n507;
assign o_15_ = ~n138;
assign o_16_ = ~n407;
assign o_17_ = ~n354;
assign o_18_ = ~n421;
assign o_19_ = ~n420;
assign o_20_ = ~n142;
assign o_21_ = ~n145;
assign o_22_ = ~n148;
assign o_23_ = ~n352;
assign o_24_ = ~n504;
assign o_25_ = ~n200;
assign o_26_ = ~n151;
assign o_27_ = ~n260;
assign o_28_ = ~n556;
assign o_29_ = ~n506;
assign o_30_ = ~n150;
assign o_31_ = ~n347;
assign o_32_ = ~n344;
assign o_33_ = ~n340;
assign o_34_ = ~n336;
assign o_35_ = ~n332;
assign o_36_ = ~n328;
assign o_37_ = ~n321;
assign o_38_ = ~n314;
assign o_39_ = ~n308;
assign o_40_ = ~n303;
assign o_41_ = ~n296;
assign o_42_ = ~n291;
assign o_43_ = ~n284;
assign o_44_ = ~n276;
assign o_45_ = ~n274;
assign o_46_ = ~n268;
assign o_47_ = ~n264;
assign o_48_ = ~n259;
assign o_49_ = ~n257;
assign o_50_ = ~n252;
assign o_51_ = ~n245;
assign o_52_ = ~n238;
assign o_53_ = ~n232;
assign o_54_ = ~n226;
assign o_55_ = ~n220;
assign o_56_ = ~n214;
assign o_57_ = ~n205;
assign o_58_ = ~n197;
assign o_59_ = ~n189;
assign o_60_ = ~n182;
assign o_61_ = ~n173;
assign o_62_ = ~n164;
assign n134 = n155 | n439;
assign n135 = n155 | n441;
assign n136 = n134 & n135;
assign n137 = n436 | n339;
assign n138 = n445 | n339;
assign n139 = n137 & n138;
assign n140 = n462 | n152;
assign n141 = n463 | n152;
assign n142 = n140 & n141;
assign n143 = n439 | n152;
assign n144 = n441 | n152;
assign n145 = n143 & n144;
assign n146 = n434 | n152;
assign n147 = n446 | n152;
assign n148 = n146 & n147;
assign n149 = n434 | n373;
assign n150 = n434 | n369;
assign n151 = n149 & n150;
assign n152 = i_2_ | ~i_0_ | i_1_;
assign n153 = n152 | ~n381;
assign n154 = ~i_3_ | ~i_4_ | ~i_5_;
assign n155 = i_0_ | i_1_ | ~i_2_;
assign n156 = n154 | n155;
assign n157 = i_0_ | i_1_ | i_2_;
assign n158 = n157 | ~n366;
assign n159 = n373 & n338;
assign n160 = n514 & n505 & n363;
assign n161 = n515 & n339 & n269 & n195 & n496;
assign n162 = n179 & n458 & n408 & n461 & n374;
assign n163 = n150 & n516 & n517 & n176 & n454;
assign n164 = n159 & n160 & n161 & n162 & n163;
assign n165 = n398 & n533 & n535;
assign n166 = n523 & n524;
assign n167 = n412 & n503;
assign n168 = n504 & n363;
assign n169 = n450 & n556;
assign n170 = n372 & n555 & n180;
assign n171 = n254 & n243 & n400;
assign n172 = n518 & n192 & n554;
assign n173 = n165 & n166 & n167 & n168 & n169 & n170 & n171 & n172;
assign n174 = n208 & n309 & n563 & n421 & n254 & n518;
assign n175 = n410 & n560 & n192 & n165 & n457 & n461 & n150 & n516;
assign n176 = n452 & n451;
assign n177 = n362 & n552 & n454;
assign n178 = n369 | n462;
assign n179 = n436 | n409;
assign n180 = n436 | n270;
assign n181 = n369 | n463;
assign n182 = n174 & n175 & n176 & n177 & n178 & n179 & n180 & n181;
assign n183 = n411 & (n157 | ~n382) & n412;
assign n184 = n548 & n298;
assign n185 = n418 & (n239 | n409);
assign n186 = n569 & n570 & n310 & n345 & n169 & n334 & n255 & n163;
assign n187 = n265 & n573 & n170 & n203;
assign n188 = n594 & n493 & n487 & n483 & n408 & n397 & ~n383 & n387;
assign n189 = n183 & n184 & n185 & n186 & n187 & n188;
assign n190 = n576 & n575 & n532 & n451 & n414 & n140 & n297 & ~n367;
assign n191 = n493 & ~n383 & n492;
assign n192 = n405 & n550 & n404 & n145 & n551 & n549;
assign n193 = n563 & n272;
assign n194 = n421 & n485 & n487;
assign n195 = n478 & n481 & n475 & n477;
assign n196 = n351 & n158 & (n154 | n157);
assign n197 = n190 & n191 & n192 & n193 & n194 & n195 & n138 & n196;
assign n198 = n470 & n468;
assign n199 = n150 & n536;
assign n200 = n270 | n443;
assign n201 = n261 & n471 & n394;
assign n202 = n228 & n414 & (n339 | ~n382);
assign n203 = n179 & n572;
assign n204 = n221 & n215 & n422 & n185 & n423 & n300;
assign n205 = n198 & n199 & n200 & n201 & n166 & n202 & n203 & n204;
assign n206 = n578 & n579 & n554 & n169;
assign n207 = n310 & n577;
assign n208 = n496 & n562;
assign n209 = n580 & ~n395 & n491;
assign n210 = n149 & n378 & n370 & n419 & n306;
assign n211 = n501 & n563;
assign n212 = n180 & n518;
assign n213 = n228 & n171 & n467 & n196 & n594 & n376 & n534 & n471;
assign n214 = n206 & n207 & n208 & n209 & n210 & n211 & n212 & n213;
assign n215 = n563 & n183;
assign n216 = n537 & ~n367 & n451;
assign n217 = n534 & n275 & n139 & n142;
assign n218 = n570 & n571 & n184 & n581 & n337 & n582;
assign n219 = n156 & n171 & n427 & n200;
assign n220 = n215 & n216 & n180 & n166 & n217 & n218 & n219;
assign n221 = n396 & n180 & n159;
assign n222 = n474 & n247;
assign n223 = n519 & n348 & n494;
assign n224 = n472 & n470;
assign n225 = n572 & n575 & n478 & n538 & n158 & n458 & n534 & n468;
assign n226 = n209 & n219 & n193 & n221 & n222 & n223 & n224 & n225;
assign n227 = n449 & n452;
assign n228 = n525 & n526;
assign n229 = n146 & n527 & n528 & n529 & n530;
assign n230 = n391 & n392 & (n393 | n339);
assign n231 = n476 & n583 & n537 & n137 & n141 & n534;
assign n232 = n174 & n218 & n227 & n228 & n229 & n230 & n231;
assign n233 = n351 & n215;
assign n234 = n254 & n494 & n559 & n509 & n262 & n292 & n426;
assign n235 = n387 & n491;
assign n236 = n384 & n385 & (n373 | n386);
assign n237 = n510 & n548;
assign n238 = n233 & n234 & n224 & n235 & n236 & n186 & n162 & n237;
assign n239 = ~n381 & ~n382;
assign n240 = n155 | n239;
assign n241 = n255 & n240 & n389 & n387 & n584 & n491;
assign n242 = n488 & n489;
assign n243 = n421 & n482;
assign n244 = n254 & n494 & n453;
assign n245 = n175 & n212 & n227 & n233 & n241 & n242 & n243 & n244;
assign n246 = n560 & n203;
assign n247 = n408 & ((~n381 & ~n382) | n409);
assign n248 = n200 & n483 & n486;
assign n249 = n540 & n539;
assign n250 = n524 & n192 & n412 & n501 & n168 & n288 & n293;
assign n251 = n535 & n543 & n546 & n477 & n380 & n533;
assign n252 = n246 & n247 & n248 & n249 & n250 & n251;
assign n253 = n288 & n248 & n342 & n586 & n266;
assign n254 = n155 | n446;
assign n255 = n155 | n443;
assign n256 = n350 & n158 & n351 & n520;
assign n257 = n193 & n235 & n253 & n254 & n255 & n256;
assign n258 = n254 & n241 & n135 & n134;
assign n259 = n258 & n253 & n242 & n160;
assign n260 = n443 | n339;
assign n261 = n434 | n339;
assign n262 = n429 & n281 & n248;
assign n263 = n417 & n224 & (n393 | n270);
assign n264 = n260 & n190 & n139 & n261 & n262 & n250 & n263;
assign n265 = n421 & n156 & n468 & n200;
assign n266 = n210 & n585 & n345 & n207;
assign n267 = n196 & n496 & n160 & n396 & n180 & n515;
assign n268 = n265 & n191 & n206 & n263 & n266 & n267;
assign n269 = n493 & n492 & n194 & n196 & ~n383;
assign n270 = i_2_ | i_0_ | ~i_1_;
assign n271 = n260 & n261;
assign n272 = n500 & n330 & n420 & n411 & n497 & n498;
assign n273 = n577 & n206 & n210;
assign n274 = n269 & n168 & n270 & n271 & n272 & n217 & n273;
assign n275 = n530 & n568 & n146 & n529;
assign n276 = n211 & n273 & n161 & n275;
assign n277 = n567 & n530 & n482 & ~n415 & n137 & n228 & ~n395;
assign n278 = n196 & n330 & n451 & n431 & n254 & n491 & n588 & n589;
assign n279 = n484 & n363 & n486 & n502;
assign n280 = n180 & (n270 | n355);
assign n281 = n476 & n583 & n468 & n396;
assign n282 = n298 & n417 & n222;
assign n283 = n511 & n405 & n499 & n508 & n374 & n377 & n179 & n595;
assign n284 = n277 & n278 & n249 & n279 & n280 & n281 & n282 & n283;
assign n285 = n477 & n394 & n471 & n378;
assign n286 = n413 & n423 & n590 & n138 & n144 & n228;
assign n287 = n179 & n553;
assign n288 = n422 & n243;
assign n289 = n419 & n420 & n579;
assign n290 = n549 & n406 & n410 & n563 & n569 & n411 & n380 & n596;
assign n291 = n285 & n286 & n248 & n278 & n287 & n288 & n289 & n290;
assign n292 = n288 & n404 & (n152 | ~n366);
assign n293 = n326 & n426 & n258;
assign n294 = n585 & n586 & n345 & n248;
assign n295 = n547 & n405 & n560 & n542 & n543 & n546;
assign n296 = n292 & n293 & n294 & n193 & n207 & n223 & n295;
assign n297 = n458 & n246 & n247;
assign n298 = n402 & n547;
assign n299 = n356 & n550 & n564;
assign n300 = n254 & n400 & n543;
assign n301 = n405 & n318 & n473 & n536 & n476 & n469 & n474 & n409;
assign n302 = n482 & n411 & n153 & n339 & n380 & n330 & n523;
assign n303 = n275 & n297 & n298 & n299 & n300 & n279 & n301 & n302;
assign n304 = n573 & n185 & n581 & n587 & n315 & n167 & n203 & n591;
assign n305 = n153 & n531;
assign n306 = n356 & n564 & n184;
assign n307 = n470 & n142 & n145 & n194 & n261 & ~n382;
assign n308 = n277 & n285 & n304 & n305 & n306 & n258 & n307;
assign n309 = n196 & n492 & n561;
assign n310 = n142 & n275 & ~n415;
assign n311 = n149 & n298 & n419;
assign n312 = n147 & n370 & n508;
assign n313 = n327 & n503 & n363;
assign n314 = n309 & n310 & n206 & n294 & n311 & n312 & n208 & n313;
assign n315 = n575 & n576 & n457 & n454;
assign n316 = n448 & n513 & n459;
assign n317 = n447 & n512 & n136 & n145 & n526 & n495 & n460;
assign n318 = n525 & n478 & n481;
assign n319 = n405 & n562 & n578 & n230 & n532 & n371;
assign n320 = n541 & n556 & n147 & n449 & n510 & n551 & n565 & n597;
assign n321 = n315 & n316 & n317 & n211 & n234 & n318 & n319 & n320;
assign n322 = n477 & n550 & n342 & n318 & n311 & n471 & n470 & n592;
assign n323 = n146 & n590;
assign n324 = n561 & n548 & n531 & n491 & ~n382 & n387;
assign n325 = n356 & n507;
assign n326 = n242 & n256;
assign n327 = n482 & n254;
assign n328 = n322 & n323 & n193 & n324 & n325 & n326 & n327 & n194;
assign n329 = n325 & n353 & (n152 | ~n381);
assign n330 = n515 & n495;
assign n331 = n531 & n486 & n485;
assign n332 = n243 & n293 & n322 & n323 & n329 & n330 & n211 & n331;
assign n333 = n143 & (n152 | ~n382);
assign n334 = n416 & (n270 | ~n366) & n417;
assign n335 = n518 & n398 & n243 & n180 & n254 & n508;
assign n336 = n286 & n304 & n324 & n298 & n333 & n334 & n335;
assign n337 = n572 & n578 & n287;
assign n338 = n152 & n511 & n312 & n402 & n512 & n513;
assign n339 = ~i_2_ | i_0_ | ~i_1_;
assign n340 = n216 & n301 & n211 & n337 & n338 & n208 & n339 & n269;
assign n341 = n550 & n311 & n329;
assign n342 = n206 & n223;
assign n343 = n180 & n482;
assign n344 = n279 & n341 & n258 & n342 & n326 & n272 & n165 & n343;
assign n345 = n202 & n413 & n567;
assign n346 = n523 & n505 & n229 & n305 & n330 & n363 & ~n415;
assign n347 = n345 & n206 & n171 & n334 & n224 & n262 & n341 & n346;
assign n348 = n157 | n370;
assign n349 = n519 & n520;
assign n350 = n154 | n157;
assign n351 = n445 | n157;
assign n352 = n348 & n349 & n350 & n351;
assign n353 = n152 | ~n366;
assign n354 = n153 & n353;
assign n355 = n435 | n442;
assign n356 = n442 | n444;
assign n357 = n355 & n356;
assign n358 = n157 | n462;
assign n359 = n488 & n515 & n178 & n552 & n316 & n396 & n486 & n593;
assign n360 = (~n366 & ~n381) | n438;
assign n361 = n143 & n358 & n134 & n140 & n359 & n360;
assign n362 = n409 | n463;
assign n363 = n358 & n506;
assign n364 = n468 & n483 & n489 & n142 & n509 & n465;
assign n365 = n181 & n362 & n363 & n317 & n359 & n364;
assign n366 = i_3_ & i_4_ & ~i_5_;
assign n367 = ~n369 & (~n154 | n366);
assign n368 = n369 | (n356 & n378);
assign n369 = ~i_0_ | ~i_1_ | ~i_2_;
assign n370 = n438 | n444;
assign n371 = n368 & (n369 | n370);
assign n372 = n445 | n373;
assign n373 = ~i_2_ | ~i_0_ | i_1_;
assign n374 = n372 & ((n154 & ~n366) | n373);
assign n375 = n339 | n239;
assign n376 = n464 & n465;
assign n377 = n376 & (n270 | n154);
assign n378 = n440 | n444;
assign n379 = n270 | (n356 & n378);
assign n380 = n180 & (n270 | ~n381);
assign n381 = ~i_5_ & ~i_3_ & i_4_;
assign n382 = i_5_ & ~i_3_ & i_4_;
assign n383 = ~n155 & (n381 | n382);
assign n384 = n373 | n355;
assign n385 = n436 | n373;
assign n386 = n435 | n440;
assign n387 = n155 | n436;
assign n388 = n387 & (n155 | ~n381);
assign n389 = n155 | (n355 & n386);
assign n390 = ~n157 & (~n154 | n366);
assign n391 = n378 | n339;
assign n392 = n140 & n138 & n566;
assign n393 = n154 & ~n366;
assign n394 = n260 & n376 & (n393 | n270);
assign n395 = ~n339 & (n381 | n382);
assign n396 = n270 | n439;
assign n397 = n396 & (n270 | ~n382);
assign n398 = n198 & n397 & (n270 | ~n381);
assign n399 = n155 | ~n382;
assign n400 = n136 & (n239 | n155);
assign n401 = n369 | (n355 & n386);
assign n402 = n443 | n373;
assign n403 = n435 | n438;
assign n404 = n149 & n402 & (n373 | n403);
assign n405 = n236 & (n239 | n373);
assign n406 = n372 & (n393 | n373);
assign n407 = n409 | n445;
assign n408 = n459 & n460;
assign n409 = ~i_0_ | ~i_1_ | i_2_;
assign n410 = n407 & n408 & (n393 | n409);
assign n411 = n436 | n157;
assign n412 = n157 | ~n381;
assign n413 = n137 & (n339 | ~n381);
assign n414 = n391 & n565 & n534;
assign n415 = ~n339 & (~n154 | n366);
assign n416 = n271 & n377;
assign n417 = n471 & n379;
assign n418 = n407 & n455 & n456;
assign n419 = n385 & (n373 | ~n381);
assign n420 = n412 & (n157 | ~n382);
assign n421 = n155 | ~n366;
assign n422 = n421 & (n155 | n154);
assign n423 = n339 | (n239 & n393);
assign n424 = n373 | n393;
assign n425 = n155 | (n356 & n378);
assign n426 = n425 & (n155 | n370);
assign n427 = n434 | n270;
assign n428 = n270 | (n386 & n403);
assign n429 = n280 & n427 & n428;
assign n430 = n409 | (n434 & n443);
assign n431 = n386 & n355 & n430;
assign n432 = i_3_ | i_4_ | i_5_;
assign n433 = ~i_6_ | ~i_7_;
assign n434 = n432 | n433;
assign n435 = i_3_ | i_4_ | ~i_5_;
assign n436 = n433 | n435;
assign n437 = i_5_ | ~i_3_ | i_4_;
assign n438 = i_6_ | i_7_;
assign n439 = n437 | n438;
assign n440 = i_6_ | ~i_7_;
assign n441 = n437 | n440;
assign n442 = ~i_6_ | i_7_;
assign n443 = n432 | n442;
assign n444 = ~i_5_ | ~i_3_ | i_4_;
assign n445 = n433 | n444;
assign n446 = n433 | n437;
assign n447 = n369 | n441;
assign n448 = n369 | n439;
assign n449 = n369 | n446;
assign n450 = n437 | n442;
assign n451 = n447 & n448 & n449 & n450;
assign n452 = n436 | n369;
assign n453 = n369 | n445;
assign n454 = ~n367 & n453;
assign n455 = n409 | n356;
assign n456 = n409 | n378;
assign n457 = n409 | n446;
assign n458 = n457 & n418;
assign n459 = n439 | n409;
assign n460 = n441 | n409;
assign n461 = n403 & n431;
assign n462 = n432 | n438;
assign n463 = n432 | n440;
assign n464 = n339 | n462;
assign n465 = n339 | n463;
assign n466 = n403 | n339;
assign n467 = n466 & n271;
assign n468 = n270 | n441;
assign n469 = n468 & n396;
assign n470 = n270 | n446;
assign n471 = n270 | n445;
assign n472 = n270 | n370;
assign n473 = n470 & n379 & n471 & n472;
assign n474 = n270 | ~n366;
assign n475 = n474 & n473;
assign n476 = n270 | ~n382;
assign n477 = n476 & n469;
assign n478 = n377 & n467;
assign n479 = n386 | n339;
assign n480 = n355 | n339;
assign n481 = n479 & n375 & n137 & n480;
assign n482 = n155 | n445;
assign n483 = n270 | n463;
assign n484 = n427 & n200 & n483;
assign n485 = n484 & n380;
assign n486 = n270 | n462;
assign n487 = n486 & n156;
assign n488 = n155 | n462;
assign n489 = n155 | n463;
assign n490 = n255 & n242;
assign n491 = n434 | n155;
assign n492 = n387 & n491 & n490;
assign n493 = n136 & n327;
assign n494 = n446 | n157;
assign n495 = n441 | n157;
assign n496 = n494 & n495;
assign n497 = n355 | n157;
assign n498 = n386 | n157;
assign n499 = n411 & n497 & n498;
assign n500 = n403 | n157;
assign n501 = n500 & n499;
assign n502 = n434 | n157;
assign n503 = n502 & n501;
assign n504 = n443 | n157;
assign n505 = n412 & n504 & n503;
assign n506 = n157 | n463;
assign n507 = n445 | n152;
assign n508 = n378 & n325;
assign n509 = n441 | n373;
assign n510 = n439 | n373;
assign n511 = n509 & n510;
assign n512 = n373 | n463;
assign n513 = n373 | n462;
assign n514 = n157 | ~n382;
assign n515 = n439 | n157;
assign n516 = n369 | n443;
assign n517 = n393 | n409;
assign n518 = n486 & n156 & n484;
assign n519 = n378 | n157;
assign n520 = n356 | n157;
assign n521 = n584 & n491 & n255;
assign n522 = n521 & n489 & n488 & n349 & n351 & n388 & n389 & ~n390;
assign n523 = n494 & n522;
assign n524 = n514 & n330;
assign n525 = n439 | n339;
assign n526 = n441 | n339;
assign n527 = n355 | n152;
assign n528 = n386 | n152;
assign n529 = n403 | n152;
assign n530 = n443 | n152;
assign n531 = n436 | n152;
assign n532 = n141 & n229 & n305;
assign n533 = n137 & n201 & ~n395;
assign n534 = n446 | n339;
assign n535 = n230 & n532 & n534 & n228;
assign n536 = n516 & n181 & n178;
assign n537 = n239 | n369;
assign n538 = n537 & n451 & n454 & n401 & n371;
assign n539 = n407 & n455;
assign n540 = ~n366 | n409;
assign n541 = n409 | n370;
assign n542 = n540 & n408 & n539 & n456 & n541 & n457;
assign n543 = n452 & n538;
assign n544 = n369 | n403;
assign n545 = n154 | n409;
assign n546 = n544 & n545 & n199;
assign n547 = n513 & n512;
assign n548 = n154 | n152;
assign n549 = n325 & n547 & n353 & n548;
assign n550 = n147 & n378 & n370;
assign n551 = n152 | ~n382;
assign n552 = n409 | n462;
assign n553 = n239 | n409;
assign n554 = n543 & n546 & n461 & n542 & n552 & n553 & n179 & n362;
assign n555 = n373 | ~n382;
assign n556 = n446 | n373;
assign n557 = n356 | n373;
assign n558 = n378 | n373;
assign n559 = n373 | n370;
assign n560 = n511 & n169 & n406 & n557 & n558 & n559;
assign n561 = n136 & ~n383;
assign n562 = n515 & n514 & n412;
assign n563 = n502 & n168;
assign n564 = n507 & n353;
assign n565 = n339 | n370;
assign n566 = n356 | n339;
assign n567 = n138 & n566;
assign n568 = n531 & n527 & n528;
assign n569 = n153 & n333;
assign n570 = n144 & n299;
assign n571 = n149 & n419;
assign n572 = n362 & n552 & n461;
assign n573 = n326 & n571 & n524 & n168;
assign n574 = n452 & n537 & n401;
assign n575 = n517 & n199;
assign n576 = n544 & n574;
assign n577 = n153 & n333 & n144 & n147;
assign n578 = n558 & n424 & n372 & n557;
assign n579 = n509 & n510 & n555;
assign n580 = n350 & n490;
assign n581 = n169 & n579;
assign n582 = n473 & n536 & n569 & n150 & n458 & n271;
assign n583 = n270 | ~n381;
assign n584 = n155 | n403;
assign n585 = n466 & n416 & n480 & n479;
assign n586 = n429 & n281 & n263;
assign n587 = n534 & n494;
assign n588 = n457 & n261 & n470;
assign n589 = n580 & n587 & n568 & n574 & n536 & n177 & n388 & n400;
assign n590 = n142 & n530;
assign n591 = n451 & n408 & n374;
assign n592 = n145 & n339 & n474;
assign n593 = n510 & n525 & n464;
assign n594 = n239 | n270;
assign n595 = n545 & n260;
assign n596 = n151 & n402 & n427;
assign n597 = n418 & n475 & n522 & n534 & n348 & n399;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:32:57 2019
module misex3 (
a, b, c, d, e, f, g, h, i, j, k, l, m, n,
r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2 );
input a, b, c, d, e, f, g, h, i, j, k, l, m, n;
output r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2;
wire n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505,
n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762;
assign r2 = ~n293;
assign s2 = ~n74;
assign t2 = ~n217;
assign u2 = ~n148;
assign n2 = ~n68;
assign o2 = ~n62;
assign p2 = ~n388;
assign q2 = ~n349;
assign h2 = ~n56;
assign i2 = ~n569;
assign j2 = ~n55;
assign k2 = ~n50;
assign m2 = ~n456;
assign l2 = ~n757 | ~n759 | n46 | ~n747 | n44 | n45 | n42 | n43;
assign n42 = f & (~n680 | ~n739 | ~n740);
assign n43 = ~f & (n475 | n476 | ~n735);
assign n44 = ~n & (~n722 | ~n724 | ~n728);
assign n45 = n & (~n518 | ~n730 | ~n731);
assign n46 = n548 | ~n744 | n544 | n547 | n542 | ~n543 | ~n540 | n541;
assign n47 = n675 | n676 | n372 | i | l;
assign n48 = n438 | n549 | n189;
assign n49 = n434 & n662 & n661 & n51 & n437 & n439;
assign n50 = n49 & n47 & n48;
assign n51 = n657 & n573 & n656 & n431 & n425 & n428;
assign n52 = n443 & n442 & n440 & n441;
assign n53 = n675 | n189 | n438;
assign n54 = n179 | n480 | n550 | n551;
assign n55 = n54 & n53 & n51 & n52;
assign n56 = n579 & n578 & n577 & n576 & n575 & n574 & n572 & n573;
assign n57 = (n95 | n408) & (n409 | n88);
assign n58 = n96 | n121;
assign n59 = n648 & ~n404 & n361 & n402;
assign n60 = n83 | n317;
assign n61 = (n362 | n300) & (n363 | n426);
assign n62 = ~n416 & ~n415 & ~n414 & n61 & n60 & n59 & n57 & n58;
assign n63 = j | n243 | n119 | n591;
assign n64 = (n177 | n362) & (n684 | n409);
assign n65 = ~n297 & (n95 | n253 | n298);
assign n66 = n620 & n619 & n572 & n618 & n617 & n69 & n574 & n211;
assign n67 = ~n422 & (n591 | (n710 & n711));
assign n68 = ~n420 & ~n419 & n67 & n66 & n65 & n64 & n59 & n63;
assign n69 = n92 | n407 | n91;
assign n70 = n595 | n92;
assign n71 = n264 | ~d | n248;
assign n72 = n701 & (n236 | n79);
assign n73 = n232 & (n152 | n632);
assign n74 = ~n267 & ~n266 & ~n265 & n73 & n72 & n71 & n69 & n70;
assign n75 = ~h | ~k;
assign n76 = n75 | l;
assign n77 = n623 | ~n658;
assign n78 = ~n167 & (n77 | ~n586);
assign n79 = ~c | n459;
assign n80 = e | n521;
assign n81 = n612 & n302;
assign n82 = n81 & n79 & n80;
assign n83 = ~k | n199;
assign n84 = m | j | ~l;
assign n85 = n83 & (~n | n84);
assign n86 = n684 | n83;
assign n87 = (n192 | n605) & (n206 | n604);
assign n88 = ~g | n603;
assign n89 = n86 & n87 & (n85 | n88);
assign n90 = (n110 | n156) & (n113 | n275);
assign n91 = ~i | n538;
assign n92 = ~a | n521;
assign n93 = n90 & (n91 | n92);
assign n94 = ~g | n600;
assign n95 = n285 & n397;
assign n96 = ~k | n167;
assign n97 = n96 | n94 | n95;
assign n98 = n601 | n199;
assign n99 = ~i | n368;
assign n100 = n98 & (~n | n99);
assign n101 = ~h | n538;
assign n102 = ~n | n129;
assign n103 = h | n538;
assign n104 = (n100 | n103) & (n101 | n102);
assign n105 = ~g | n249;
assign n106 = h | n197;
assign n107 = (n100 | n106) & (n102 | n105);
assign n108 = ~k | n179;
assign n109 = n108 & (n | n84);
assign n110 = n608 & n287 & n607;
assign n111 = (n101 | n92) & (n110 | n105);
assign n112 = n135 | n119;
assign n113 = n218 & n295;
assign n114 = ~g | n393;
assign n115 = n112 & n111 & (n113 | n114);
assign n116 = (n110 | n164) & (n113 | n189);
assign n117 = e | n609;
assign n118 = n116 & (n92 | n117);
assign n119 = ~a | n271;
assign n120 = ~e | n609;
assign n121 = n118 & (n119 | n120);
assign n122 = (n110 | n106) & (n113 | n202);
assign n123 = n122 & (n92 | n103);
assign n124 = n153 | n399;
assign n125 = ~n610 | ~g | n237;
assign n126 = j | n154;
assign n127 = ~i | n609;
assign n128 = n124 & n125 & (n126 | n127);
assign n129 = n401 & n512 & n527 & n760;
assign n130 = (n106 | n99) & (n129 | n105);
assign n131 = n519 | ~i | n121;
assign n132 = (n123 | n588) & (n95 | n128);
assign n133 = ~e | n271;
assign n134 = n131 & n132 & (n130 | n133);
assign n135 = ~h | n243;
assign n136 = h | n243;
assign n137 = (n100 | n136) & (n135 | n102);
assign n138 = ~n137 & (~n625 | (b & ~n479));
assign n139 = ~n89 & (~n325 | ~n606);
assign n140 = ~n167 & (~n683 | (~n121 & ~n601));
assign n141 = ~n95 & (~n687 | (~n96 & ~n127));
assign n142 = n133 | n601 | n179 | n106;
assign n143 = n590 | n591;
assign n144 = n136 | n587 | n588;
assign n145 = ~n139 & ~n140 & (n | n134);
assign n146 = (n93 | n591) & (n104 | n616);
assign n147 = n688 & (n107 | n269);
assign n148 = n147 & n146 & n145 & n144 & n143 & n142 & n66 & ~n138;
assign n149 = n689 | n108;
assign n150 = (n372 | n193) & (n613 | n624);
assign n151 = ~f | n603;
assign n152 = n149 & n150 & (n109 | n151);
assign n153 = ~m | n611;
assign n154 = ~l | ~m;
assign n155 = n153 & (i | n154);
assign n156 = ~i | n197;
assign n157 = j | n197;
assign n158 = n156 & n157;
assign n159 = (n155 | n105) & (n158 | n589);
assign n160 = n690 & (n164 | n126);
assign n161 = n644 & n647;
assign n162 = i | n197;
assign n163 = n159 & n160 & (n161 | n162);
assign n164 = g | n249;
assign n165 = (n164 | n96) & (n | n163);
assign n166 = n75 | ~m | n;
assign n167 = ~m | n;
assign n168 = ~l | ~h | j;
assign n169 = n166 & (n167 | n168);
assign n170 = ~f | n243;
assign n171 = ~e | n196;
assign n172 = (n169 | n171) & (~n78 | n170);
assign n173 = n196 | d | n169;
assign n174 = d | n197;
assign n175 = n173 & (~n78 | n174);
assign n176 = j | n75;
assign n177 = n176 & (i | n75);
assign n178 = n299 & n300 & n76 & n177;
assign n179 = m | n;
assign n180 = j | n603;
assign n181 = ~l | n179;
assign n182 = (n180 | n181) & (n178 | n179);
assign n183 = ~e | n615;
assign n184 = ~n | n183;
assign n185 = (n99 | n184) & (n98 | n183);
assign n186 = ~n184 & ~n761 & (~n114 | ~n189);
assign n187 = ~n186 & (n185 | (n202 & n676));
assign n188 = n183 | n391;
assign n189 = g | n393;
assign n190 = n187 & (n188 | (n114 & n189));
assign n191 = (n206 | n624) & (n689 | n83);
assign n192 = k | n199;
assign n193 = ~j | n249;
assign n194 = n191 & (n192 | n193);
assign n195 = n194 & (n85 | n151);
assign n196 = ~f | g;
assign n197 = ~f | ~g;
assign n198 = (n169 | n196) & (~n78 | n197);
assign n199 = m | ~n;
assign n200 = ~l | n199;
assign n201 = (n180 | n200) & (n178 | n199);
assign n202 = h | n570;
assign n203 = (n100 | n202) & (n102 | n114);
assign n204 = n203 & (n201 | (n170 & n171));
assign n205 = n691 & n692 & (n85 | n314);
assign n206 = l | n199;
assign n207 = ~k | n393;
assign n208 = n89 & n205 & (n206 | n207);
assign n209 = ~n152 & (~n133 | ~n430);
assign n210 = n595 | n599;
assign n211 = n595 | n353;
assign n212 = n693 & (~e | n195 | n324);
assign n213 = ~n209 & (n285 | (n165 & n595));
assign n214 = n208 | n315;
assign n215 = (n172 | n119) & (n175 | n287);
assign n216 = n694 & (n182 | n302);
assign n217 = n216 & n190 & n215 & n214 & n213 & n212 & n210 & n211;
assign n218 = ~a | n560;
assign n219 = n167 | n218;
assign n220 = (n168 | n219) & (n218 | n166);
assign n221 = ~n658 | ~n586 | n623;
assign n222 = ~f & ~n538;
assign n223 = ~n219 & n221 & (n222 | ~n261);
assign n224 = e | n488;
assign n225 = e | n196;
assign n226 = ~n223 & (n220 | (n224 & n225));
assign n227 = n393 | ~j | n372;
assign n228 = (n613 | n207) & (n109 | n314);
assign n229 = n640 & n643;
assign n230 = n227 & n228 & (n229 | n108);
assign n231 = ~e | n626;
assign n232 = n190 & n226 & (n230 | n231);
assign n233 = ~n83 & (~n252 | ~n639);
assign n234 = (n192 | n322) & (n256 | n206);
assign n235 = g | n603;
assign n236 = ~n233 & n234 & (n85 | n235);
assign n237 = k | n154;
assign n238 = (i | n161) & (~j | n237);
assign n239 = ~n591 & (~n91 | (~j & ~n538));
assign n240 = ~n239 & (n | (n699 & n700));
assign n241 = n165 & n240 & (n96 | n117);
assign n242 = ~i | n243;
assign n243 = ~e | ~g;
assign n244 = n242 & (j | n243);
assign n245 = n96 | n120;
assign n246 = n697 & (n120 | n126);
assign n247 = n696 & n695 & (n244 | n589);
assign n248 = n245 & (n | (n246 & n247));
assign n249 = ~f | ~h;
assign n250 = n249 | n102 | e;
assign n251 = n629 & n88;
assign n252 = j | n609;
assign n253 = i | n602;
assign n254 = ~g | n360;
assign n255 = n254 & n253 & n251 & n252;
assign n256 = g | n75;
assign n257 = n698 & (n376 | (n628 & n649));
assign n258 = (n94 | n96) & (n629 | n630);
assign n259 = ~l | n167;
assign n260 = n257 & n258 & (n255 | n259);
assign n261 = ~f | n538;
assign n262 = (n169 | n225) & (~n78 | n261);
assign n263 = ~n260 & (~n655 | (d & ~n524));
assign n264 = a | ~b;
assign n265 = ~n201 & (~n325 | (~n261 & ~n616));
assign n266 = ~n352 & (~n262 | n263);
assign n267 = ~n526 & (~n250 | (~n100 & ~n631));
assign n268 = n344 & (n83 | n633);
assign n269 = ~b | n598;
assign n270 = n268 & (n194 | n269);
assign n271 = ~c | d;
assign n272 = n79 & (~f | n271);
assign n273 = (n100 | n634) & (n164 | n102);
assign n274 = n273 & n107;
assign n275 = ~i | n570;
assign n276 = j | n570;
assign n277 = n275 & n276;
assign n278 = (n155 | n114) & (n277 | n589);
assign n279 = n749 & (n189 | n126);
assign n280 = i | n570;
assign n281 = n278 & n279 & (n161 | n280);
assign n282 = (n96 | n189) & (n | n281);
assign n283 = n286 | g | n169;
assign n284 = n283 & (d | ~n78 | n243);
assign n285 = ~e | n264;
assign n286 = d | ~e;
assign n287 = c | ~a | ~b;
assign n288 = n285 & (n286 | n287);
assign n289 = (n236 | n635) & (n104 | n616);
assign n290 = (n260 | n288) & (n284 | ~n545);
assign n291 = n107 | n315;
assign n292 = (n182 | n272) & (n274 | n625);
assign n293 = n292 & n291 & n290 & n289 & n270 & n232;
assign n294 = n123 & (n119 | n136);
assign n295 = n596 & n594;
assign n296 = n112 & n111 & (n295 | n114);
assign n297 = ~n636 & (~n355 | (~n167 & ~n296));
assign n298 = n | n126;
assign n299 = ~h | n360;
assign n300 = ~k | n603;
assign n301 = n180 & n300 & n299 & n176;
assign n302 = ~c | n524;
assign n303 = n302 & (~c | n196);
assign n304 = (n113 | n646) & (~j | n645);
assign n305 = ~j | n197;
assign n306 = n304 & (n110 | n305);
assign n307 = n121 & (n95 | n94);
assign n308 = ~n95 & ~n644 & (~n88 | ~n660);
assign n309 = ~n308 & (n329 | n339 | n435);
assign n310 = (n118 | n126) & (n306 | n237);
assign n311 = ~l | n519;
assign n312 = n309 & n310 & (n307 | n311);
assign n313 = n183 & n390;
assign n314 = f | n603;
assign n315 = ~b | n286;
assign n316 = (n314 | n315) & (n313 | n235);
assign n317 = n633 & n316;
assign n318 = (n80 & (~n | n371)) | (n & n371);
assign n319 = (n88 | n318) & (~n | n317);
assign n320 = n393 | ~j | n315;
assign n321 = n269 | n193;
assign n322 = ~j | n609;
assign n323 = n320 & n321 & (n313 | n322);
assign n324 = b | ~c;
assign n325 = ~f | n324;
assign n326 = (n315 | n643) & (n313 | n252);
assign n327 = j | n249;
assign n328 = n326 & (n269 | n327);
assign n329 = ~h | n621;
assign n330 = n328 & (n325 | n329);
assign n331 = (n316 | n84) & (n330 | n435);
assign n332 = m | k | ~l;
assign n333 = n331 & (n323 | n332);
assign n334 = (n315 | n640) & (n313 | n639);
assign n335 = i | n249;
assign n336 = n334 & (n269 | n335);
assign n337 = ~n199 & (~n336 | (~n253 & ~n371));
assign n338 = ~n337 & (n80 | n179 | n253);
assign n339 = n303 & n637;
assign n340 = (n339 | n181) & (n325 | n200);
assign n341 = ~n318 & (~n704 | (~n332 & ~n605));
assign n342 = n243 | n490 | ~j | n119;
assign n343 = n298 | n119 | n120;
assign n344 = n633 | ~n | n84;
assign n345 = n705 & (n301 | n340);
assign n346 = n65 & (n319 | n435);
assign n347 = (n312 & (~n | n333)) | (n & n333);
assign n348 = (n682 | n641) & (n338 | n433);
assign n349 = n348 & n347 & n346 & n345 & n344 & n343 & ~n341 & n342;
assign n350 = (n113 | n280) & (i | n645);
assign n351 = n350 & (n110 | n162);
assign n352 = ~a | n324;
assign n353 = ~b | n597;
assign n354 = n353 & n287 & n352;
assign n355 = n114 | n219;
assign n356 = (n599 | n105) & (n295 | n114);
assign n357 = n112 & (n92 | (n105 & n101));
assign n358 = n355 & (n167 | (n356 & n357));
assign n359 = n707 & (n285 | n630 | n605);
assign n360 = ~j | k;
assign n361 = n359 & (n358 | n360);
assign n362 = (n339 | n179) & (n325 | n199);
assign n363 = (n339 | n108) & (n325 | n83);
assign n364 = ~n88 & (~n706 | (~n167 & ~n433));
assign n365 = ~n364 & (n629 | (n259 & n630));
assign n366 = n365 & (n96 | n322);
assign n367 = n519 | n | n121;
assign n368 = ~k | m;
assign n369 = (n253 | n318) & (~n | n336);
assign n370 = n367 & (n368 | (n369 & n319));
assign n371 = n395 & n315 & n606;
assign n372 = k | n179;
assign n373 = (n372 | n80) & (n371 | n192);
assign n374 = ~i | k | ~l | n167;
assign n375 = ~k | ~n610;
assign n376 = l | n167;
assign n377 = n374 & (n375 | (n376 & n259));
assign n378 = ~j | n603;
assign n379 = n378 & n329;
assign n380 = n644 | n587 | n627;
assign n381 = n647 | n587 | n627;
assign n382 = n351 | n | n161;
assign n383 = (n294 | n377) & (n363 | n379);
assign n384 = n373 | n605;
assign n385 = (n95 | n366) & (~j | n370);
assign n386 = n362 | n299;
assign n387 = n361 & (n323 | n192);
assign n388 = n387 & n386 & n385 & n384 & n383 & n382 & n380 & n381;
assign n389 = ~n372 & (~n303 | ~n637);
assign n390 = n635 & n638;
assign n391 = ~n | n401;
assign n392 = n188 & (n390 | n391);
assign n393 = f | ~h;
assign n394 = (n393 | n315) & (n249 | n269);
assign n395 = n616 & n625;
assign n396 = e | n324;
assign n397 = ~b | n524;
assign n398 = n397 & n396 & n395 & n315;
assign n399 = ~i | n602;
assign n400 = (n398 | n399) & (~i | n394);
assign n401 = m | n360;
assign n402 = n399 | n | n80 | n401;
assign n403 = h & n610;
assign n404 = n403 & (n389 | (~n192 & ~n325));
assign n405 = n253 | n641;
assign n406 = (n256 | n167) & (n376 | n176);
assign n407 = n | n592;
assign n408 = n405 & n406 & (n407 | n399);
assign n409 = (n108 | n80) & (n371 | n83);
assign n410 = i & ~n394;
assign n411 = n & (n410 | (~n127 & ~n313));
assign n412 = j | i;
assign n413 = n412 | ~k | n259;
assign n414 = ~n115 & (~n413 | (n77 & ~n167));
assign n415 = ~n527 & (n411 | (~n318 & ~n399));
assign n416 = ~n591 & (~n709 | (~n110 & ~n327));
assign n417 = ~n433 & (~n351 | (~n119 & ~n627));
assign n418 = ~n311 & ~n & ~n251;
assign n419 = ~n95 & (n418 | (~n376 & ~n649));
assign n420 = ~n83 & (~n328 | ~n336);
assign n421 = i & k;
assign n422 = ~n167 & (n417 | (~n294 & n421));
assign n423 = n654 | ~f | n598;
assign n424 = j | k;
assign n425 = n259 | n399 | n423 | n424;
assign n426 = ~h | n600;
assign n427 = n651 | ~n | n557;
assign n428 = n427 | n426 | n332;
assign n429 = n650 | n114 | n181;
assign n430 = ~e | n521;
assign n431 = n429 | n430;
assign n432 = ~n545 | n655;
assign n433 = ~l | ~j | ~k;
assign n434 = n399 | n167 | n432 | n433;
assign n435 = ~l | n368;
assign n436 = n170 | n526;
assign n437 = n436 | ~n403 | n435;
assign n438 = n181 | n375;
assign n439 = n438 | n231 | n105;
assign n440 = n652 | n202 | n632;
assign n441 = ~n653 | n435 | n445;
assign n442 = n181 | n202 | n430 | ~n473;
assign n443 = n712 & (n332 | n427 | n378);
assign n444 = n106 | n613 | n231 | n658;
assign n445 = h | n621;
assign n446 = m | k | l;
assign n447 = n444 & (n436 | n445 | n446);
assign n448 = n551 | n | n446;
assign n449 = n448 & (n179 | n127 | n433);
assign n450 = k | n189 | n181 | n632;
assign n451 = n332 | n651 | ~h | n224;
assign n452 = n450 & n451;
assign n453 = n641 | n654 | n660 | n477;
assign n454 = n105 | n181 | n549 | n650;
assign n455 = (n449 | n480) & (n452 | n412);
assign n456 = n455 & n454 & n453 & n49 & n52 & n447;
assign n457 = i | n179;
assign n458 = (~k | n457) & (n179 | ~n412);
assign n459 = e | ~f;
assign n460 = a | n526;
assign n461 = j & ~n630 & (n459 | n460);
assign n462 = ~n758 & (~h | n438 | ~n479);
assign n463 = f | ~c | e;
assign n464 = ~n461 & n462 & (n458 | n463);
assign n465 = b | n199;
assign n466 = n200 & n83 & n465 & n298;
assign n467 = (b | n200) & (c | n181);
assign n468 = ~n167 & (~n737 | (~b & ~n479));
assign n469 = h | j | n199;
assign n470 = (j | n83) & (~i | n663);
assign n471 = ~j | n199;
assign n472 = n469 & n470 & (~h | n471);
assign n473 = ~k & n610;
assign n474 = n473 & b & ~n199;
assign n475 = ~h & (n474 | (~i & ~n206));
assign n476 = ~n673 & (~n521 | (~e & n324));
assign n477 = f | n659;
assign n478 = n477 & (f | a | e);
assign n479 = c | d;
assign n480 = f | n479;
assign n481 = n669 | c | e;
assign n482 = b | e | ~n | n669;
assign n483 = n375 | ~n615 | ~h | n259;
assign n484 = (d | n734) & (n457 | n480);
assign n485 = n199 | n675;
assign n486 = ~n762 & n485 & n484 & n483 & n481 & n482;
assign n487 = c & ~n655;
assign n488 = f | g;
assign n489 = b | n488;
assign n490 = n | n237;
assign n491 = (j | n490) & (n199 | ~n626);
assign n492 = ~n199 & (~n741 | (~j & ~n525));
assign n493 = n742 & (n670 | n671);
assign n494 = ~n492 & ~n756 & (i | n491);
assign n495 = n493 & n494 & (n457 | n271);
assign n496 = c | n488;
assign n497 = n664 & n463;
assign n498 = (n106 | n231) & (~j | n497);
assign n499 = (n716 | n167) & (n498 | n179);
assign n500 = n496 | n372;
assign n501 = (n527 | n671) & (n719 | n613);
assign n502 = n718 & (n436 | (n206 & n192));
assign n503 = n502 & n501 & n499 & n500;
assign n504 = ~j & ~n372 & (~n271 | ~n302);
assign n505 = (b | n199) & (c | n179);
assign n506 = ~b | ~e | ~n | n666;
assign n507 = e | n505 | n650;
assign n508 = (n525 | n471) & (n457 | n479);
assign n509 = n478 | n167;
assign n510 = ~n626 | j | n192;
assign n511 = n510 & n509 & n508 & n507 & ~n504 & n506;
assign n512 = i | n368;
assign n513 = m | n603;
assign n514 = i | m;
assign n515 = n512 & n513 & (~l | n514);
assign n516 = n253 & n127;
assign n517 = (n426 | n446) & (n516 | n666);
assign n518 = n517 & (n401 | n151);
assign n519 = ~k | ~m;
assign n520 = n519 & (j | ~m);
assign n521 = c | ~d;
assign n522 = n81 & (g | n521);
assign n523 = ~n311 & n403 & (~n174 | ~n261);
assign n524 = ~e | f;
assign n525 = b | n524;
assign n526 = ~d | n615;
assign n527 = j | n368;
assign n528 = n99 & n527;
assign n529 = n717 & (h | n524 | n636);
assign n530 = (n521 | n525) & (~j | n716);
assign n531 = (i | n432) & (n254 | n665);
assign n532 = n634 & n550 & (n135 | n650);
assign n533 = n532 & n531 & n529 & n530;
assign n534 = ~c & ~n524;
assign n535 = (~n180 | ~n628) & (~n463 | n534);
assign n536 = ~j & (~n660 | (~n156 & ~n231));
assign n537 = n396 & (a | c | e);
assign n538 = e | ~g;
assign n539 = ~n162 & (~n108 | ~n181);
assign n540 = n375 | n259 | n114;
assign n541 = ~n489 & (~n206 | ~n663);
assign n542 = ~n613 & (~n497 | (~c & ~n660));
assign n543 = n438 | n101;
assign n544 = ~n231 & (n539 | (~n156 & ~n613));
assign n545 = a & ~n615;
assign n546 = n545 & ~n655 & (~n630 | ~n672);
assign n547 = ~n457 & (~n631 | (~n105 & ~n231));
assign n548 = ~n179 & (n535 | n536 | ~n715);
assign n549 = ~e | n479;
assign n550 = l | n424;
assign n551 = i | g | h;
assign n552 = n112 | n155 | n;
assign n553 = n119 | n245;
assign n554 = f | n167;
assign n555 = (n168 | n554) & (f | n166);
assign n556 = n555 | ~e | g;
assign n557 = f | n243;
assign n558 = n556 & (~n78 | n557);
assign n559 = ~n99 & ~g & n;
assign n560 = ~b | ~d;
assign n561 = (n203 | n560) & (n526 | ~n748);
assign n562 = (n175 | n287) & (n282 | n594);
assign n563 = n236 | n638;
assign n564 = (n352 | n558) & (~e | n561);
assign n565 = n608 | n172;
assign n566 = n677 & n553 & n552 & n342 & n143 & n63;
assign n567 = n226 & n270 & (n89 | n625);
assign n568 = n750 & n752 & n656 & n661 & n441 & n657 & n440 & n662;
assign n569 = n568 & n567 & n447 & n566 & n565 & n564 & n562 & n563;
assign n570 = f | ~g;
assign n571 = (g | n555) & (~n78 | n570);
assign n572 = n595 | n352;
assign n573 = n652 | n106 | n549;
assign n574 = n593 | n596;
assign n575 = n626 | ~a | n262;
assign n576 = n571 | ~d | ~n545;
assign n577 = n753 & (n654 | (n175 & n248));
assign n578 = n282 | n596;
assign n579 = n566 & (n165 | n352);
assign n580 = l | ~n421;
assign n581 = ~l | ~h | i;
assign n582 = (~l & n622) | (n603 & (l | n622));
assign n583 = ~h | n611;
assign n584 = ~l | n360;
assign n585 = ~l | n621;
assign n586 = n585 & n584 & n583 & n582 & n580 & n581;
assign n587 = n | n119;
assign n588 = ~i | n154;
assign n589 = l | n519;
assign n590 = n119 | n242;
assign n591 = n | n589;
assign n592 = j | n519;
assign n593 = n407 | n275;
assign n594 = ~a | n286;
assign n595 = n156 | n407;
assign n596 = ~e | ~a | ~c;
assign n597 = d | a;
assign n598 = ~d | e;
assign n599 = ~a | n598;
assign n600 = ~i | j;
assign n601 = ~l | n600;
assign n602 = ~g | ~h;
assign n603 = h | ~i;
assign n604 = ~g | n75;
assign n605 = ~j | n602;
assign n606 = n396 & n397;
assign n607 = n599 & n353;
assign n608 = n92 & n352;
assign n609 = g | ~h;
assign n610 = i & j;
assign n611 = ~j | l;
assign n612 = ~f | n521;
assign n613 = l | n179;
assign n614 = ~g | ~n421;
assign n615 = ~b | ~c;
assign n616 = d | n615;
assign n617 = n590 | n407;
assign n618 = n593 | n594;
assign n619 = n97 & n70 & n210;
assign n620 = (n595 | n287) & (n593 | n218);
assign n621 = i | ~j;
assign n622 = j | ~k;
assign n623 = k & ~n600;
assign n624 = ~k | n249;
assign n625 = ~b | n521;
assign n626 = ~c | ~d;
assign n627 = i | n243;
assign n628 = n614 & n605;
assign n629 = ~g | n621;
assign n630 = k | n167;
assign n631 = h | n459;
assign n632 = e | n626;
assign n633 = n269 | n151;
assign n634 = h | n196;
assign n635 = ~b | n459;
assign n636 = ~l | n412;
assign n637 = n612 & n272;
assign n638 = ~f | n560;
assign n639 = i | n609;
assign n640 = i | n393;
assign n641 = n622 | ~l | n167;
assign n642 = j | n602;
assign n643 = j | n393;
assign n644 = ~j | n154;
assign n645 = n538 | n92;
assign n646 = ~j | n570;
assign n647 = ~m | n360;
assign n648 = (n392 | n127) & (n400 | n391);
assign n649 = ~g | n622;
assign n650 = k | n600;
assign n651 = b | n626;
assign n652 = n621 | ~k | n181;
assign n653 = n222 & ~n526;
assign n654 = a | n615;
assign n655 = ~f | ~d | ~e;
assign n656 = ~n653 | n332 | n426;
assign n657 = n632 | n429;
assign n658 = k | n621;
assign n659 = d | e;
assign n660 = i | ~g | h;
assign n661 = n445 | n435 | n427;
assign n662 = n430 | n202 | n652;
assign n663 = n83 & n471;
assign n664 = ~g | n479;
assign n665 = a | n598;
assign n666 = m | n424;
assign n667 = ~h | n514;
assign n668 = k | n514;
assign n669 = h | n514;
assign n670 = m | n600;
assign n671 = n | n479;
assign n672 = h | n167;
assign n673 = g | n199;
assign n674 = h & ~n650;
assign n675 = e | n479;
assign n676 = h | n488;
assign n677 = n343 & n144 & n454 & n617 & n381 & n380;
assign n678 = (e & ~n119) | (~n92 & (~e | ~n119));
assign n679 = (n479 & n674) | (~g & (~n479 | n674));
assign n680 = n755 & (i | n466 | h);
assign n681 = ~n610 | l | n115;
assign n682 = n590 & n93;
assign n683 = n681 & (n682 | n584);
assign n684 = n642 & n253;
assign n685 = (n684 | n108) & (n109 | n88);
assign n686 = (n605 | n372) & (n604 | n613);
assign n687 = (n614 | n376) & (n88 | n259);
assign n688 = ~n141 & (n82 | (n685 & n686));
assign n689 = n335 & n327;
assign n690 = (n588 | n106) & (n237 | n305);
assign n691 = n229 | n83;
assign n692 = n393 | ~j | n192;
assign n693 = ~a | b | ~d | n198;
assign n694 = (n607 | n165) & (n204 | n625);
assign n695 = (n161 | n627) & (n155 | n135);
assign n696 = n243 | ~j | n237;
assign n697 = (n588 | n136) & (n242 | n592);
assign n698 = n256 | n167;
assign n699 = (n155 | n101) & (n238 | n538);
assign n700 = (n588 | n103) & (n117 | n126);
assign n701 = (n182 | n612) & (n241 | n92);
assign n702 = ~n294 & (~n585 | (l & n610));
assign n703 = ~n95 & (~n252 | ~n254 | ~n256);
assign n704 = (n84 | n88) & (n642 | n435);
assign n705 = (n167 | ~n702) & (n259 | ~n703);
assign n706 = n490 & (n96 | n611);
assign n707 = n354 | n360 | n167 | n105;
assign n708 = ~h | j;
assign n709 = (n113 | n643) & (~n678 | n708);
assign n710 = (n95 | n88) & (j | n645);
assign n711 = (n110 | n157) & (n113 | n276);
assign n712 = n167 | n127 | n584 | n423;
assign n713 = (d | n525) & (j | n436);
assign n714 = (b | c) & (n127 | n433);
assign n715 = (n253 | n463) & (n103 | ~n473);
assign n716 = n676 & n478;
assign n717 = a | b;
assign n718 = n433 | n487 | ~h | n199;
assign n719 = n496 & ~n534;
assign n720 = n478 & n665 & n432;
assign n721 = ~n523 & (g | n520 | n720);
assign n722 = n721 & (n670 | (n496 & n480));
assign n723 = (n522 | n669) & (n164 | n666);
assign n724 = n723 & (n668 | (n202 & n664));
assign n725 = n231 | n156 | n401;
assign n726 = n592 | n432;
assign n727 = n725 & n726 & (n719 | n667);
assign n728 = n518 & n727 & (n496 | n515);
assign n729 = (n436 | n667) & (n525 | n528);
assign n730 = n729 & (n515 | n436);
assign n731 = (n669 | n397) & (n525 | n668);
assign n732 = n526 | e | n472;
assign n733 = n672 | ~n597 | n636;
assign n734 = n754 & (~h | n438);
assign n735 = n732 & n733 & (~c | n734);
assign n736 = n | a | ~g;
assign n737 = (i | n665) & (~n545 | n659);
assign n738 = ~n468 & (n311 | ~n403 | n736);
assign n739 = n738 & (n665 | (n672 & n96));
assign n740 = (n549 | n673) & (n179 | ~n679);
assign n741 = n489 & (e | n254);
assign n742 = ~n629 | k | n206;
assign n743 = ~n546 & (n537 | n554);
assign n744 = n743 & (n199 | (n714 & n713));
assign n745 = (n720 | n376) & (n533 | n167);
assign n746 = (n192 | n327) & (~i | n503);
assign n747 = n745 & n746 & (n591 | n445);
assign n748 = ~h & (n559 | (~n601 & ~n673));
assign n749 = (n588 | n202) & (n237 | n646);
assign n750 = n53 & n47 & n618;
assign n751 = n526 | n102 | n120;
assign n752 = n751 & (n651 | (n104 & n195));
assign n753 = n449 | n480;
assign n754 = ~n473 | h | n179;
assign n755 = n467 | ~h | n375;
assign n756 = i & ~k & (~n376 | ~n613);
assign n757 = (n495 & (~h | n511)) | (h & n511);
assign n758 = ~h & (~n96 | (c & ~n457));
assign n759 = (n464 & (~g | n486)) | (g & n486);
assign n760 = l | n368;
assign n761 = n760 & n512 & n527;
assign n762 = n674 & ~n167 & n460;
endmodule

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// Benchmark "s298.bench" written by ABC on Tue Mar 5 10:03:54 2019
module s298 ( clock,
G0, G1, G2,
G117, G132, G66, G118, G133, G67 );
input G0, G1, G2, clock;
output G117, G132, G66, G118, G133, G67;
reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23;
wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1,
n56_1, n61_1, n66_2, n71_1, n76_1, n81_1, n86_1;
assign n21_1 = ~G0 & ~G10;
assign n26_1 = ~G0 & (G10 ? (~G11 & (G12 | ~G13)) : G11);
assign n31_1 = ~G0 & ((G12 & (~G10 | ~G11)) | (G10 & G11 & ~G12));
assign n36_1 = ~G0 & ((G11 & ((~G12 & G13) | (G10 & G12 & ~G13))) | (G13 & (~G10 | (~G11 & G12))));
assign n41_1 = ~G0 & (G14 ^ (G23 | (G10 & G13 & n57)));
assign n57 = ~G11 & ~G12;
assign n46_1 = ~G0 & ~n59;
assign n59 = (G11 & (~G15 | (~G12 & G13 & ~G14 & ~G22))) | (~G15 & (G12 | ~G13 | G14 | ~G22));
assign n51_1 = n59 & ((G13 & (~G14 | G16)) | (G12 & G14 & G16));
assign n56_1 = n59 & ((~G13 & (G11 ? ~G12 : ~G14)) | (G14 & G17 & (G12 | G13)));
assign n61_1 = n59 & ((G14 & G18 & (G12 | G13)) | (~G13 & (~G14 | (G11 & ~G12))));
assign n66_2 = n59 ? n64 : ~G10;
assign n64 = (G13 & (~G14 | G19)) | (G14 & ((~G11 & ~G12 & ~G13) | (G12 & G19)));
assign n71_1 = n59 ? (n66 & (G20 | (~G12 & ~G13))) : ~G10;
assign n66 = G14 & (~G11 | G12 | G13);
assign n76_1 = n59 & ((G12 & ((G11 & ~G13 & ~G14) | (G14 & G21))) | (G13 & G14 & G21));
assign n81_1 = ~G0 & (G2 ^ G22);
assign n86_1 = ~G0 & (G1 ^ G23);
assign G117 = G18;
assign G132 = G20;
assign G66 = G16;
assign G118 = G19;
assign G133 = G21;
assign G67 = G17;
always @ (posedge clock) begin
G10 <= n21_1;
G11 <= n26_1;
G12 <= n31_1;
G13 <= n36_1;
G14 <= n41_1;
G15 <= n46_1;
G16 <= n51_1;
G17 <= n56_1;
G18 <= n61_1;
G19 <= n66_2;
G20 <= n71_1;
G21 <= n76_1;
G22 <= n81_1;
G23 <= n86_1;
end
initial begin
G10 <= 1'b0;
G11 <= 1'b0;
G12 <= 1'b0;
G13 <= 1'b0;
G14 <= 1'b0;
G15 <= 1'b0;
G16 <= 1'b0;
G17 <= 1'b0;
G18 <= 1'b0;
G19 <= 1'b0;
G20 <= 1'b0;
G21 <= 1'b0;
G22 <= 1'b0;
G23 <= 1'b0;
end
endmodule

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**************************************************************************************************
* Example VTR experiments complete with scripts, benchmarks, architectures, and expected results
**************************************************************************************************
Starting out:
basic_flow - Run the whole VTR flow to map a simple Verilog circuit to an FPGA architecture
Advanced (Flagshp experiment):
timing - Run the flagship VTR benchmarks on our comprehensive, realistic architecture file
timing_chain - Same as above but this time with carry chains
Legacy:
regression_mcnc - Run VTR on the historical MCNC benchmarks on a legacy architecture file
(Note: This is only useful for comparing to the past, it is not realistic in the modern world)
Custom, unique logic blocks:
regression_titan\titan_small - Simplified Altera Stratix IV (commercial FPGA) architecture capture
regression_fpu_hard_block_arch - Custom hard FPU logic block architecture

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# Standard Configuration Example
[CAD_TOOLS_PATH]
yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc
abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr
ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
iverilog_path = iverilog
include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists
[FLOW_SCRIPT_CONFIG]
valid_flows = standard,vtr,vtr_standard,yosys_vpr
[DEFAULT_PARSE_RESULT_VPR]
# parser format <name of variable> = <regex string>, <lambda function/type>
clb_blocks = "Netlist clb blocks: ([0-9]+)", str
logic_delay = "Total logic delay: ([0-9.]+)", str
total_net_delay = "total net delay: ([0-9.]+)", str
total_routing_area = "Total routing area: ([0-9.]+)", str
total_logic_block_area = "Total used logic block area: ([0-9]+)", str
total_wire_length = "Total wirelength: ([0-9]+)", str
packing_time = "Packing took ([0-9.]+) seconds", str
placement_time = "Placement took ([0-9.]+) seconds", str
routing_time = "Routing took ([0-9.]+) seconds", str
average_net_length = "average net length: ([0-9.]+)", str
critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific
total_time_taken = "Routing took ([0-9.]+) seconds", float
[DEFAULT_PARSE_RESULT_POWER]
pb_type_power="PB Types\s+([0-9]+)", str
routing_power="Routing\s+([0-9]+)", str
switch_box_power="Switch Box\s+([0-9]+)", str
connection_box_power="Connection Box\s+([0-9]+)", str
primitives_power="Primitives\s+([0-9]+)", str
interc_structures_power="Interc Structures\s+([0-9]+)", str
lut6_power="^\s+lut6\s+([0-9]+)", str
ff_power="^\s+ff\s+([0-9]+)", str
[INTERMIDIATE_FILE_PREFIX]
# Yosys files
yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif
yosys_output=yosys_output.txt
# ACE2 and intermidiate file
activity_file=${PATH:TOP_MODULE}_ace_out.act
ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif
corrected_format_blif=${PATH:TOP_MODULE}.blif
blackbox_blif=${PATH:TOP_MODULE}_bb.blif
# VPR Files
min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt
reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt
fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt
vpr_stat_parse_fn=vpr_stat.txt
vpr_power_stat_parse_fn=vpr_power_stat.txt
vpr_net_file=${PATH:TOP_MODULE}_vpr.net
vpr_place_file=${PATH:TOP_MODULE}_vpr.place
vpr_route_file=${PATH:TOP_MODULE}_vpr.route
#Iverilog verification file
iverilog_output=iverilog_output.txt
vvp_output=vvp_sim_output.txt
[CMD_ARGUMENT_DEPENDANCY]
vpr_fpga_verilog=vpr_fpga_verilog_dir|abc
vpr_fpga_verilog_dir=vpr_fpga_verilog

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# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
# Technology mapping
hierarchy -top ${TOP_MODULE}
proc
techmap -D NO_LUT -map +/adff2dff.v
# Synthesis
synth -top ${TOP_MODULE} -flatten
clean
# LUT mapping
abc -lut ${LUT_SIZE}
# Check
synth -run check
# Clean and output blif
opt_clean -purge
write_blif ${OUTPUT_BLIF}

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#!usr/bin/perl -w
use strict;
#use Shell;
use FileHandle;
#Use the time
use Time::gmtime;
#Get Date
my $mydate = gmctime();
my ($char_per_line) = (80);
my ($fname,$frpt,$finitial);
my $add_default_clk = "off";
my $latch_token;
my ($remove_buffers) = (0);
my ($default_clk_name) = ("clk");
my @buffers_to_remove;
my @buffers_to_rename;
sub print_usage()
{
print "Usage:\n";
print " perl <script_name.pl> [-options]\n";
print " Options:(Mandatory!)\n";
print " -i <input_blif_path>\n";
print " -o <output_blif_path>\n";
print " Options: (Optional)\n";
print " -remove_buffers\n";
print " -add_default_clk\n";
print " -initial_blif <input_blif_path>\n";
print "\n";
return 0;
}
sub opts_read()
{
if (-1 == $#ARGV) {
print "Error: No input argument!\n";
&print_usage();
exit(1);
} else {
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) {
if ("-i" eq $ARGV[$iargv]) {
$fname = $ARGV[$iargv+1];
} elsif ("-o" eq $ARGV[$iargv]) {
$frpt = $ARGV[$iargv+1];
} elsif ("-add_default_clk" eq $ARGV[$iargv]) {
$add_default_clk = "on";
} elsif ("-initial_blif" eq $ARGV[$iargv]) {
$finitial = $ARGV[$iargv+1];
} elsif ("-remove_buffers" eq $ARGV[$iargv]) {
$remove_buffers = 1;
}
}
}
return 0;
}
# Print a line of blif netlist
sub fprint_blifln($ $ $) {
my ($FH, $tokens_ref, $char_per_line) = @_;
my ($cur_line_len) = (0);
my @tokens = @$tokens_ref;
if ($char_per_line < 1) {
die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n";
}
# if the length of current line exceed the char_per_line,
# A continue line '\' is added and start a new line
for (my $itok = 0; $itok < ($#tokens+1); $itok++) {
if (!($tokens[$itok])) {
next;
}
# Contain any buffer names to be removed won't show up
if (1 == $remove_buffers) {
for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) {
$tokens[$itok] = $buffers_to_rename[$ibuf];
}
}
}
$cur_line_len += length($tokens[$itok]);
if ($cur_line_len > $char_per_line) {
print $FH "\\"."\n";
$cur_line_len = 0;
}
print $FH "$tokens[$itok] ";
$cur_line_len += length($tokens[$itok]);
}
print $FH "\n";
}
sub read_blifline($ $) {
my ($FIN, $line_no_ptr) = @_;
my ($lines,$line) = ("","");
# Get one line
if (defined($line = <$FIN>)) {
chomp $line;
$lines = $line;
# Replace the < and > with [ and ], VPR does not support...
$lines =~ s/</[/g;
$lines =~ s/>/]/g;
while($lines =~ m/\\$/) {
$lines =~ s/\\$//;
if (defined($line = <$FIN>)) {
chomp $line;
$lines = $lines.$line;
$line =~ s/</[/g;
$line =~ s/>/]/g;
} else {
return $lines;
}
}
return $lines;
} else {
return $lines;
}
}
sub process_blifmodel($ $) {
my ($FIN,$line_no_ptr) = @_;
my ($blackbox) = (0);
my ($lines);
my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0);
my @model_input_tokens;
my ($input_lines);
while(!eof($FIN)) {
# Get one line
$lines = &read_blifline($FIN,$line_no_ptr);
# Check the tokens
if (!defined($lines)) {
next;
}
my @tokens = split('\s+',$lines);
# .end -> return
if (!defined($tokens[0])) {
next;
}
if (".end" eq $tokens[0]) {
return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
} elsif (".inputs" eq $tokens[0]) {
foreach my $temp(@tokens) {
if ($temp eq $default_clk_name) {
$have_default_clk = 1;
$clk_num++;
print "Found 1 clock: $temp in @tokens\n";
last;
}
}
@model_input_tokens = @tokens;
} elsif (".blackbox" eq $tokens[0]) {
$blackbox = 1;
} elsif (".latch" eq $tokens[0]) {
# illegal definition exit
if ((3 != $#tokens)&&(5 != $#tokens)) {
die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n";
} elsif (3 == $#tokens) {
# We need a default clock
if ($need_default_clk == 0) {
$need_default_clk = 1;
$clk_num++;
}
} elsif (5 == $#tokens) {
$clk_recorded = 0;
# Check if we have this clk names already
foreach my $tmp(@model_input_tokens) {
if ($tmp eq $tokens[4]) {
$clk_recorded = 1;
last;
}
}
# if have been recorded, we push it into the array
if (0 == $clk_recorded) {
$clk_num++;
push @model_input_tokens,$tokens[4];
}
}
# Could be subckt or .names
} elsif (".names" eq $tokens[0]) {
if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
# We want to know is this a buffer???
my $lut_lines = &read_blifline($FIN,$line_no_ptr);
my @lut_lines_tokens = split('\s+',$lut_lines);
if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
# push it to the array: buffers_to_remove
push @buffers_to_remove,$tokens[1];
push @buffers_to_rename,$tokens[2];
}
}
}
}
# Re-organise the input lines
#print @model_input_tokens;
$input_lines = ".inputs ";
foreach my $temp(@model_input_tokens) {
if (".inputs" ne $temp) {
$input_lines .= $temp." ";
}
}
$input_lines =~ s/\s+$//;
@model_input_tokens = split('\s+',$input_lines);
return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
}
sub scan_blif()
{
my ($line,$lines);
my @tokens;
my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded);
my ($blackbox,$model_clk_num);
my @input_tokens;
my $input_lines;
my (@input_buffer);
my ($line_no) = (0);
if (!defined($finitial)) {
$latch_token = "re clk";
} else {
my $latch_token_found = 0;
my $count = 0;
my ($FIN0) = FileHandle->new;
if ($FIN0->open("< $finitial")) {
print "INFO: Parsing $finitial...\n";
} else {
die "ERROR: Fail to open $finitial!\n";
}
while((!$latch_token_found)&&(!eof($FIN0))){
# Get one line
$lines = &read_blifline($FIN0);
if (!defined($lines)) {
next;
}
@tokens = split('\s+',$lines);
if(".latch" eq $tokens[0]) {
if($#tokens == 5){
$latch_token = "$tokens[3] $tokens[4]";
$latch_token_found = 1;
}
}
}
close($FIN0);
}
# Pre-process the netlist
# Open src file first-scan to check if we have clock
my ($FIN) = FileHandle->new;
if ($FIN->open("< $fname")) {
print "INFO: Parsing $fname...\n";
} else {
die "ERROR: Fail to open $fname!\n";
}
while(!eof($FIN)) {
# Get one line
$lines = &read_blifline($FIN);
if (!defined($lines)) {
next;
}
@tokens = split('\s+',$lines);
if (!defined($tokens[0])) {
next;
}
# When we found .model we should check it. until .end comes.
# Check if it is a black box
if (".model" eq $tokens[0]) {
($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no);
if (0 == $blackbox) {
@input_tokens = @$input_lines;
}
$clk_num += $model_clk_num;
}
}
close($FIN);
# Add default clock
if ("on" eq $add_default_clk) {
print "INFO: $clk_num clock ports need to be added.\n";
print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n";
if ((0 == $have_default_clk)&&(1 == $need_default_clk)) {
push @input_tokens,$default_clk_name;
}
}
# Bypass some sensitive tokens
for(my $itok = 0; $itok < $#input_tokens+1; $itok++) {
if ("unconn" eq $input_tokens[$itok]) {
delete $input_tokens[$itok];
}
}
# Print Buffer names to be removed
my $num_buffer_to_remove = $#buffers_to_remove + 1;
print "INFO: $num_buffer_to_remove buffer to be removed:\n";
for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) {
print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n";
}
# Second scan - write
my ($inputs_written) = (0);
my ($FIN2) = FileHandle->new;
if ($FIN2->open("< $fname")) {
print "INFO: Parsing $fname the second time...\n";
} else {
die "ERROR: Fail to open $fname!\n";
}
# Open des file
my ($FOUT) = (FileHandle->new);
if (!($FOUT->open("> $frpt"))) {
die "Fail to create output file: $frpt!\n";
}
while(!eof($FIN2)) {
$line = <$FIN2>;
chomp $line;
if ($line eq "") {
print $FOUT "\n";
next;
}
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
# Check if this line start with ".latch", which we cares only
@tokens = split('\s+',$line);
if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) {
$lines = $line;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
}
#print @input_tokens."\n";
&fprint_blifln($FOUT,\@input_tokens,$char_per_line);
$inputs_written = 1;
next;
}
if (".outputs" eq $tokens[0]) {
$lines = $line;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
}
my @output_tokens = split('\s',$lines);
for(my $itok = 0; $itok < $#output_tokens+1; $itok++) {
if ("unconn" eq $output_tokens[$itok]) {
delete $output_tokens[$itok];
}
}
&fprint_blifln($FOUT,\@output_tokens,$char_per_line);
next;
}
if (".latch" eq $tokens[0]) {
# check if we need complete it
if ($#tokens == 3) {
# Complete it
for (my $i=0; $i<3; $i++) {
print $FOUT "$tokens[$i] ";
}
print $FOUT "$latch_token $tokens[3]\n";
} elsif ($#tokens == 5) {
# replace the clock name with clk
for (my $i=0; $i < ($#tokens+1); $i++) {
# if (4 == $i) {
# print $FOUT "clk ";
# } else {
print $FOUT "$tokens[$i] ";
# }
}
print $FOUT "\n";
} else {
die "ERROR: [LINE: $line_no]illegal definition of latch!\n";
}
next;
} elsif (".names" eq $tokens[0]) {
if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
# We want to know is this a buffer???
my $lut_lines = &read_blifline($FIN2,\$line_no);
my @lut_lines_tokens = split('\s+',$lut_lines);
if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
# pass it.
next;
} else {
print $FOUT "$line\n";
print $FOUT "$lut_lines\n";
}
} else {
print $FOUT "$line\n";
}
next;
} elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) {
$lines = $line;
$lines =~ s/\s+$//;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
$lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!!
}
my @subckt_tokens = split('\s+',$lines);
for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) {
if (($itok > 1)&&("" ne $subckt_tokens[$itok])) {
my @port_tokens = split('=',$subckt_tokens[$itok]);
for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) {
$port_tokens[1] = $buffers_to_rename[$ibuf];
}
}
$subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]);
#print "See:".$subckt_tokens[$itok]."\n";
}
}
&fprint_blifln($FOUT,\@subckt_tokens,$char_per_line);
next;
}
print $FOUT "$line\n";
}
close($FIN2);
close($FOUT);
return 0;
}
sub main()
{
&opts_read();
&scan_blif();
return 0;
}
&main();
exit(0);

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import os
import sys
import shutil
import time
import shlex
import glob
import argparse
from configparser import ConfigParser, ExtendedInterpolation
import logging
import glob
import subprocess
import threading
from string import Template
import re
import xml.etree.ElementTree as ET
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Initialise general paths for the script
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Copy directory where flow file exist
flow_script_dir = os.path.dirname(os.path.abspath(__file__))
# Find OpenFPGA base directory
openfpga_base_dir = os.path.abspath(
os.path.join(flow_script_dir, os.pardir, os.pardir))
# Copy directory from where script is laucnhed
# [req to resolve relative paths provided while launching script]
launch_dir = os.getcwd()
# Path section to append in configuration file to interpolate path
script_env_vars = {"PATH": {
"OPENFPGA_FLOW_PATH": flow_script_dir,
"OPENFPGA_PATH": openfpga_base_dir}}
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Reading command-line argument
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Helper function to provide better alignment to help print
def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60)
parser = argparse.ArgumentParser(formatter_class=formatter)
# Mandatory arguments
parser.add_argument('arch_file', type=str)
parser.add_argument('benchmark_files', type=str, nargs='+')
# Optional arguments
parser.add_argument('--top_module', type=str, default="top")
parser.add_argument('--fpga_flow', type=str, default="yosys_vpr")
parser.add_argument('--cad_tool_conf', type=str,
help="CAD tools path overrides default setting")
parser.add_argument('--run_dir', type=str,
default=os.path.join(openfpga_base_dir, 'tmp'),
help="Directory to store intermidiate file & final results")
parser.add_argument('--yosys_tmpl', type=str,
help="Alternate yosys template, generates top_module.blif")
# ACE2 and power estimation related arguments
parser.add_argument('--K', type=int,
help="LUT Size, if not specified extracted from arch file")
parser.add_argument('--power', action='store_true')
parser.add_argument('--power_tech', type=str,
help="Power tech xml file for power calculation")
parser.add_argument('--ace_d', type=float,
help="Specify the default signal density of PIs in ACE2")
parser.add_argument('--ace_p', type=float,
help="Specify the default signal probablity of PIs in ACE2")
parser.add_argument('--black_box_ace', action='store_true')
# VPR Options
parser.add_argument('--min_route_chan_width', type=float,
help="Turn on min_route_chan_width")
parser.add_argument('--max_route_width_retry', type=int, default=100,
help="Maximum iterations to perform to reroute")
parser.add_argument('--fix_route_chan_width', type=int,
help="Turn on fix_route_chan_width")
parser.add_argument('--vpr_timing_pack_off', action='store_true',
help="Turn off the timing-driven pack for vpr")
parser.add_argument('--vpr_place_clb_pin_remap', action='store_true',
help="Turn on place_clb_pin_remap in VPR")
parser.add_argument('--vpr_max_router_iteration', type=int,
help="Specify the max router iteration in VPR")
parser.add_argument('--vpr_route_breadthfirst', action='store_true',
help="Use the breadth-first routing algorithm of VPR")
parser.add_argument('--vpr_use_tileable_route_chan_width', action='store_true',
help="Turn on the conversion to " +
"tileable_route_chan_width in VPR")
# VPR - FPGA-X2P Extension
X2PParse = parser.add_argument_group('VPR-FPGA-X2P Extension')
X2PParse.add_argument('--vpr_fpga_x2p_rename_illegal_port', action='store_true',
help="Rename illegal ports option of VPR FPGA SPICE")
X2PParse.add_argument('--vpr_fpga_x2p_signal_density_weight', type=float,
help="Specify the signal_density_weight of VPR FPGA SPICE")
X2PParse.add_argument('--vpr_fpga_x2p_sim_window_size', type=float,
help="specify the sim_window_size of VPR FPGA SPICE")
# VPR - FPGA-SPICE Extension
SPParse = parser.add_argument_group('FPGA-SPICE Extension')
SPParse.add_argument('--vpr_fpga_spice', type=str,
help="Print SPICE netlists in VPR")
SPParse.add_argument('--vpr_fpga_spice_sim_mt_num', type=int,
help="Specify the option sim_mt_num of VPR FPGA SPICE")
SPParse.add_argument('--vpr_fpga_spice_print_component_tb', action='store_true',
help="Output component-level testbench")
SPParse.add_argument('--vpr_fpga_spice_print_grid_tb', action='store_true',
help="Output grid-level testbench")
SPParse.add_argument('--vpr_fpga_spice_print_top_tb', action='store_true',
help="Output full-chip-level testbench")
SPParse.add_argument('--vpr_fpga_spice_leakage_only', action='store_true',
help="Turn on leakage_only mode in VPR FPGA SPICE")
SPParse.add_argument('--vpr_fpga_spice_parasitic_net_estimation_off',
action='store_true',
help="Turn off parasitic_net_estimation in VPR FPGA SPICE")
SPParse.add_argument('--vpr_fpga_spice_testbench_load_extraction_off',
action='store_true',
help="Turn off testbench_load_extraction in VPR FPGA SPICE")
SPParse.add_argument('--vpr_fpga_spice_simulator_path', type=str,
help="Specify simulator path")
# VPR - FPGA-Verilog Extension
VeriPar = parser.add_argument_group('FPGA-Verilog Extension')
VeriPar.add_argument('--vpr_fpga_verilog', action='store_true',
help="Generator verilog of VPR FPGA SPICE")
VeriPar.add_argument('--vpr_fpga_verilog_dir', type=str,
help="path to store generated verilog files")
VeriPar.add_argument('--vpr_fpga_verilog_include_timing', action="store_true",
help="Print delay specification in Verilog files")
VeriPar.add_argument('--vpr_fpga_verilog_include_signal_init',
action="store_true",
help="Print signal initialization in Verilog files")
VeriPar.add_argument('--vpr_fpga_verilog_print_autocheck_top_testbench',
action="store_true", help="Print autochecked top-level " +
"testbench for Verilog Generator of VPR FPGA SPICE")
VeriPar.add_argument('--vpr_fpga_verilog_formal_verification_top_netlist',
action="store_true", help="Print formal top Verilog files")
VeriPar.add_argument('--vpr_fpga_verilog_include_icarus_simulator',
action="store_true", help="dd syntax and definition" +
" required to use Icarus Verilog simulator")
VeriPar.add_argument('--vpr_fpga_verilog_print_user_defined_template',
action="store_true", help="Unknown parameter")
VeriPar.add_argument('--vpr_fpga_verilog_print_report_timing_tcl',
action="store_true", help="Generate tcl script useful " +
"for timing report generation")
VeriPar.add_argument('--vpr_fpga_verilog_report_timing_rpt_path',
type=str, help="Specify path for report timing results")
VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_pnr', action="store_true",
help="Generate sdc file to constraint Hardware P&R")
VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_analysis',
action="store_true", help="Generate sdc file to do STA")
VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true",
help="Print top-level testbench for Verilog Generator " +
"of VPR FPGA SPICE")
VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb',
action="store_true", help="Print testbench" +
"for input blif file in Verilog Generator")
VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str,
help="Print modelsim " +
"simulation script", metavar="<modelsim.ini_path>")
# VPR - FPGA-Bitstream Extension
BSparse = parser.add_argument_group('FPGA-Bitstream Extension')
BSparse.add_argument('--vpr_fpga_bitstream_generator', action="store_true",
help="Generate FPGA-SPICE bitstream")
# Regression test option
RegParse = parser.add_argument_group('Regression Test Extension')
RegParse.add_argument("--end_flow_with_test", action="store_true",
help="Run verification test at the end")
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Global varaibles declaration
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Varible to store logger instance
logger = None
# arguments are parsed at the end of the script depending upon whether script
# is called externally or as a standalone
args = None
# variable to store script_configuration and cad tool paths
config, cad_tools = None, None
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Main program starts here
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
def main():
logger.debug("Script Launched in "+os.getcwd())
check_required_file()
read_script_config()
validate_command_line_arguments()
prepare_run_directory(args.run_dir)
if (args.fpga_flow == "yosys_vpr"):
logger.info('Running "yosys_vpr" Flow')
run_yosys_with_abc()
if (args.fpga_flow == "vtr"):
run_odin2()
run_abc_vtr()
if (args.fpga_flow == "vtr_standard"):
run_abc_for_standarad()
if args.power:
run_ace2()
run_pro_blif_3arg()
run_rewrite_verilog()
run_vpr()
if args.end_flow_with_test:
run_netlists_verification()
exit()
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Subroutines starts here
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
def check_required_file():
""" Function ensure existace of all required files for the script """
files_dict = {
"CAD TOOL PATH": os.path.join(flow_script_dir, os.pardir, 'misc',
'fpgaflow_default_tool_path.conf'),
}
for filename, filepath in files_dict.items():
if not os.path.isfile(filepath):
clean_up_and_exit("Not able to locate deafult file " + filename)
def read_script_config():
""" This fucntion reads default CAD tools path from configuration file """
global config, cad_tools
config = ConfigParser(interpolation=ExtendedInterpolation())
config.read_dict(script_env_vars)
default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc',
'fpgaflow_default_tool_path.conf')
config.read_file(open(default_cad_tool_conf))
if args.cad_tool_conf:
config.read_file(open(args.cad_tool_conf))
if not "CAD_TOOLS_PATH" in config.sections():
clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config")
cad_tools = config["CAD_TOOLS_PATH"]
def validate_command_line_arguments():
"""
TODO :
This funtion validates all supplied paramters
"""
logger.info("Validating commnad line arguments")
# Check if flow supported
if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"):
clean_up_and_exit("%s Flow not supported"%args.fpga_flow)
# Check if argument list is consistant
for eacharg, dependent in config.items("CMD_ARGUMENT_DEPENDANCY"):
if getattr(args, eacharg, None):
dependent = dependent.split(",")
for eachdep in dependent:
if not any([getattr(args, i, 0) for i in eachdep.split("|")]):
clean_up_and_exit("'%s' argument depends on (%s) argumets"%
(eacharg, ", ".join(dependent).replace("|", " or ")))
exit()
# Filter provided architecrue files
args.arch_file = os.path.abspath(args.arch_file)
if not os.path.isfile(args.arch_file):
clean_up_and_exit("Architecure file not found. -%s", args.arch_file)
# Filter provided benchmark files
for index, everyinput in enumerate(args.benchmark_files):
args.benchmark_files[index] = os.path.abspath(everyinput)
if os.path.isdir(args.benchmark_files[index]):
logger.warning("Skipping directory in bench %s" % everyinput)
logger.warning("Directory is not support in benchmark list" +
"use wildcard pattern to add files")
continue
for everyfile in glob.glob(args.benchmark_files[index]):
if not os.path.isfile(everyfile):
clean_up_and_exit(
"Failed to copy benchmark file-%s", args.arch_file)
# Filter provided powertech files
if args.power_tech:
args.power_tech = os.path.abspath(args.power_tech)
if not os.path.isfile(args.power_tech):
clean_up_and_exit(
"Power Tech file not found. -%s", args.power_tech)
# Expand run directory to absolute path
args.run_dir = os.path.abspath(args.run_dir)
def ask_user_quetion(condition, question):
if condition:
reply = str(input(question+' (y/n): ')).lower().strip()
if reply[:1] in ['n', 'no']:
return False
elif reply[:1] in ['y', 'yes']:
return True
else:
return ask_user_quetion(question, condition)
return True
def prepare_run_directory(run_dir):
"""
Prepares run directory to run
1. Change current directory to run_dir
2. Copy architecture XML file to run_dir
3. Copy circuit files to run_dir
"""
logger.info("Run directory : %s" % run_dir)
if os.path.isdir(run_dir):
no_of_files = len(next(os.walk(run_dir))[2])
if not ask_user_quetion((no_of_files > 100),
("[run_dir:%s] already exist and contains %d " +
"files script will remove all the file, " +
"continue? ") % (run_dir, no_of_files)):
clean_up_and_exit("Aborted by user")
else:
shutil.rmtree(run_dir)
os.makedirs(run_dir)
# Clean run_dir is created change working directory
os.chdir(run_dir)
# Create arch dir in run_dir and copy flattern architecrture file
os.mkdir("arch")
tmpl = Template(
open(args.arch_file, encoding='utf-8').read())
arch_filename = os.path.basename(args.arch_file)
args.arch_file = os.path.join(run_dir, "arch", arch_filename)
with open(args.arch_file, 'w', encoding='utf-8') as archfile:
archfile.write(tmpl.substitute(script_env_vars["PATH"]))
# Create benchmark dir in run_dir and copy flattern architecrture file
os.mkdir("benchmark")
try:
for index, eachfile in enumerate(args.benchmark_files):
args.benchmark_files[index] = shutil.copy2(
eachfile, os.path.join(os.curdir, "benchmark"))
except:
logger.exception("Failed to copy all benchmark file to run_dir")
def clean_up_and_exit(msg, clean=False):
logger.error("Current working directory : " + os.getcwd())
logger.error(msg)
logger.error("Exiting . . . . . .")
exit(1)
def run_yosys_with_abc():
"""
Execute yosys with ABC and optional blackbox support
"""
tree = ET.parse(args.arch_file)
root = tree.getroot()
try:
lut_size = max([int(pb_type.find("input").get("num_pins"))
for pb_type in root.iter("pb_type")
if pb_type.get("class") == "lut"])
logger.info("Extracted lut_size size from arch XML = %s", lut_size)
logger.info("Running Yosys with lut_size = %s", lut_size)
except:
logger.exception("Failed to extract lut_size from XML file")
clean_up_and_exit("")
args.K = lut_size
# Yosys script parameter mapping
ys_params = {
"READ_VERILOG_FILE": " \n".join([
"read_verilog -nolatches " + shlex.quote(eachfile)
for eachfile in args.benchmark_files]),
"TOP_MODULE": args.top_module,
"LUT_SIZE": lut_size,
"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
}
yosys_template = os.path.join(
cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
tmpl = Template(open(yosys_template, encoding='utf-8').read())
with open("yosys.ys", 'w') as archfile:
archfile.write(tmpl.substitute(ys_params))
try:
with open('yosys_output.txt', 'w+') as output:
process = subprocess.run([cad_tools["yosys_path"], 'yosys.ys'],
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
if process.returncode:
logger.info("Yosys failed with returncode %d",
process.returncode)
except:
logger.exception("Failed to run yosys")
clean_up_and_exit("")
logger.info("Yosys output is written in file yosys_output.txt")
def run_odin2():
pass
def run_abc_vtr():
pass
def run_abc_for_standarad():
pass
def run_ace2():
if args.black_box_ace:
with open(args.top_module+'_yosys_out.blif', 'r') as fp:
blif_lines = fp.readlines()
with open(args.top_module+'_bb.blif', 'w') as fp:
for eachline in blif_lines:
if ".names" in eachline:
input_nets = eachline.split()[1:]
if len(input_nets)-1 > args.K:
logger.error("One module in blif have more inputs" +
" than K value")
# Map CEll to each logic in blif
map_nets = (input_nets[:-1] + ["unconn"]*args.K)[:args.K]
map_nets = ["I[%d]=%s" % (indx, eachnet)
for indx, eachnet in enumerate(map_nets)]
map_nets += ["O[0]=%s\n" % input_nets[-1]]
fp.write(".subckt CELL ")
fp.write(" ".join(map_nets))
else:
fp.write(eachline)
declar_input = " ".join(["I[%d]" % i for i in range(args.K)])
model_tmpl = "\n" + \
".model CELL\n" + \
".inputs " + declar_input + " \n" + \
".outputs O[0]\n" + \
".blackbox\n" + \
".end\n"
fp.write(model_tmpl)
# Prepare ACE run command
command = [
"-b", args.top_module +
('_bb.blif' if args.black_box_ace else "_yosys_out.blif"),
"-o", args.top_module+"_ace_out.act",
"-n", args.top_module+"_ace_out.blif",
"-c", "clk",
]
command += ["-d", "%.4f" % args.ace_d] if args.ace_d else [""]
command += ["-p", "%.4f" % args.ace_d] if args.ace_p else [""]
try:
filename = args.top_module + '_ace2_output.txt'
with open(filename, 'w+') as output:
process = subprocess.run([cad_tools["ace_path"]] + command,
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
if process.returncode:
logger.info("ACE2 failed with returncode %d",
process.returncode)
except:
logger.exception("Failed to run ACE2")
clean_up_and_exit("")
logger.info("ACE2 output is written in file %s" % filename)
def run_pro_blif_3arg():
command = [
"-i", args.top_module+"_ace_out.blif",
"-o", args.top_module+".blif",
"-initial_blif", args.top_module+'_yosys_out.blif',
]
try:
filename = args.top_module+'_blif_3args_output.txt'
with open(filename, 'w+') as output:
process = subprocess.run(["perl", cad_tools["pro_blif_path"]] +
command,
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
if process.returncode:
logger.info("blif_3args script failed with returncode %d",
process.returncode)
except:
logger.exception("Failed to run blif_3args")
clean_up_and_exit("")
logger.info("blif_3args output is written in file %s" % filename)
def run_vpr():
# Run Standard VPR Flow
min_channel_width = run_standard_vpr(
args.top_module+".blif",
-1,
args.top_module+"_min_chan_width_vpr.txt")
logger.info("Standard VPR flow routed with minimum %d Channels" %
min_channel_width)
# Minimum routing channel width
if (args.min_route_chan_width):
min_channel_width *= args.min_route_chan_width
min_channel_width = int(min_channel_width)
min_channel_width += 1 if (min_channel_width % 2) else 0
logger.info(("Trying to route using %d channels" % min_channel_width) +
" (Slack of %d%%)" % ((args.min_route_chan_width-1)*100))
while(1):
res = run_standard_vpr(args.top_module+".blif",
int(min_channel_width),
args.top_module+"_reroute_vpr.txt",
route_only=True)
if res:
logger.info("Routing with channel width=%d successful" %
min_channel_width)
break
elif args.max_route_width_retry < (min_channel_width-2):
clean_up_and_exit("Failed to route within maximum " +
"iteration of channel width")
else:
logger.info("Unable to route using channel width %d" %
min_channel_width)
min_channel_width += 2
extract_vpr_stats(args.top_module+"_reroute_vpr.txt")
# Fixed routing channel width
elif args.fix_route_chan_width:
min_channel_width = run_standard_vpr(
args.top_module+".blif",
args.fix_route_chan_width,
args.top_module+"_fr_chan_width.txt")
logger.info("Fixed routing channel successfully routed with %d width" %
min_channel_width)
extract_vpr_stats(args.top_module+"_fr_chan_width.txt")
else:
extract_vpr_stats(args.top_module+"_min_chan_width.txt")
if args.power:
extract_vpr_stats(logfile=args.top_module+".power",
r_filename="vpr_power_stat",
parse_section="power")
def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
command = [cad_tools["vpr_path"],
args.arch_file,
bench_blif,
"--net_file", args.top_module+"_vpr.net",
"--place_file", args.top_module+"_vpr.place",
"--route_file", args.top_module+"_vpr.route",
"--full_stats", "--nodisp",
]
if route_only:
command += ["--route"]
# Power options
if args.power:
command += ["--power",
"--activity_file", args.top_module+"_ace_out.act",
"--tech_properties", args.power_tech]
# packer options
if args.vpr_timing_pack_off:
command += ["--timing_driven_clustering", "off"]
# channel width option
if fixed_chan_width >= 0:
command += ["--route_chan_width", "%d"%fixed_chan_width]
if args.vpr_use_tileable_route_chan_width:
command += ["--use_tileable_route_chan_width"]
# FPGA_Spice Options
if (args.power and args.vpr_fpga_spice):
command += ["--fpga_spice"]
if args.vpr_fpga_x2p_signal_density_weight:
command += ["--fpga_x2p_signal_density_weight",
args.vpr_fpga_x2p_signal_density_weight]
if args.vpr_fpga_x2p_sim_window_size:
command += ["--fpga_x2p_sim_window_size",
args.vpr_fpga_x2p_sim_window_size]
if args.vpr_fpga_spice_sim_mt_num:
command += ["--fpga_spice_sim_mt_num",
args.vpr_fpga_spice_sim_mt_num]
if args.vpr_fpga_spice_simulator_path:
command += ["--fpga_spice_simulator_path",
args.vpr_fpga_spice_simulator_path]
if args.vpr_fpga_spice_print_component_tb:
command += ["--fpga_spice_print_lut_testbench",
"--fpga_spice_print_hardlogic_testbench",
"--fpga_spice_print_pb_mux_testbench",
"--fpga_spice_print_cb_mux_testbench",
"--fpga_spice_print_sb_mux_testbench"
]
if args.vpr_fpga_spice_print_grid_tb:
command += ["--fpga_spice_print_grid_testbench",
"--fpga_spice_print_cb_testbench",
"--fpga_spice_print_sb_testbench"
]
if args.vpr_fpga_spice_print_top_tb:
command += ["--fpga_spice_print_top_testbench"]
if args.vpr_fpga_spice_leakage_only:
command += ["--fpga_spice_leakage_only"]
if args.vpr_fpga_spice_parasitic_net_estimation_off:
command += ["--fpga_spice_parasitic_net_estimation", "off"]
if args.vpr_fpga_spice_testbench_load_extraction_off:
command += ["--fpga_spice_testbench_load_extraction", "off"]
# FPGA Verilog options
if (args.power and args.vpr_fpga_verilog):
command += ["--fpga_verilog"]
if args.vpr_fpga_verilog_dir:
command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
if args.vpr_fpga_verilog_print_top_tb:
command += ["--fpga_verilog_print_top_testbench"]
if args.vpr_fpga_verilog_print_input_blif_tb:
command += ["--fpga_verilog_print_input_blif_testbench"]
if args.vpr_fpga_verilog_print_autocheck_top_testbench:
command += ["--fpga_verilog_print_autocheck_top_testbench",
args.top_module+"_output_verilog.v"]
if args.vpr_fpga_verilog_include_timing:
command += ["--fpga_verilog_include_timing"]
if args.vpr_fpga_verilog_include_signal_init:
command += ["--fpga_verilog_include_signal_init"]
if args.vpr_fpga_verilog_formal_verification_top_netlist:
command += ["--fpga_verilog_print_formal_verification_top_netlist"]
if args.vpr_fpga_verilog_print_modelsim_autodeck:
command += ["--fpga_verilog_print_modelsim_autodeck",
args.vpr_fpga_verilog_print_modelsim_autodeck]
if args.vpr_fpga_verilog_include_icarus_simulator:
command += ["--fpga_verilog_include_icarus_simulator"]
if args.vpr_fpga_verilog_print_report_timing_tcl:
command += ["--fpga_verilog_print_report_timing_tcl"]
if args.vpr_fpga_verilog_report_timing_rpt_path:
command += ["--fpga_verilog_report_timing_rpt_path",
args.vpr_fpga_verilog_report_timing_rpt_path]
if args.vpr_fpga_verilog_print_sdc_pnr:
command += ["--fpga_verilog_print_sdc_pnr"]
if args.vpr_fpga_verilog_print_user_defined_template:
command += ["--fpga_verilog_print_user_defined_template"]
if args.vpr_fpga_verilog_print_sdc_analysis:
command += ["--fpga_verilog_print_sdc_analysis"]
# FPGA Bitstream Genration options
if args.vpr_fpga_verilog_print_sdc_analysis:
command += ["--fpga_bitstream_generator"]
if args.vpr_fpga_x2p_rename_illegal_port or \
args.vpr_fpga_spice or \
args.vpr_fpga_verilog:
command += ["--fpga_x2p_rename_illegal_port"]
# Other VPR options
if args.vpr_place_clb_pin_remap:
command += ["--place_clb_pin_remap"]
if args.vpr_route_breadthfirst:
command += ["--router_algorithm", "breadth_first"]
if args.vpr_max_router_iteration:
command += ["--max_router_iterations", args.vpr_max_router_iteration]
chan_width = None
try:
with open(logfile, 'w+') as output:
output.write(" ".join(command)+"\n")
process = subprocess.run(command,
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
for line in process.stdout.split('\n'):
if "Best routing" in line:
chan_width = int(re.search(
r"channel width factor of ([0-9]+)", line).group(1))
if "Circuit successfully routed" in line:
chan_width = int(re.search(
r"a channel width factor of ([0-9]+)", line).group(1))
output.write(process.stdout)
if process.returncode:
logger.info("Standard VPR run failed with returncode %d",
process.returncode)
except (Exception, subprocess.CalledProcessError) as e:
logger.exception("Failed to run VPR")
process_failed_vpr_run(e.output)
clean_up_and_exit("")
logger.info("VPR output is written in file %s" % logfile)
return chan_width
def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
section = "DEFAULT_PARSE_RESULT_POWER" if parse_section == "power" \
else "DEFAULT_PARSE_RESULT_VPR"
vpr_log = open(logfile).read()
resultDict = {}
for name, value in config.items(section):
reg_string, filt_function = value.split(",")
match = re.search(reg_string[1:-1], vpr_log)
if match:
try:
if "lambda" in filt_function.strip():
eval("ParseFunction = "+filt_function.strip())
extract_val = ParseFunction(**match.groups())
elif filt_function.strip() == "int":
extract_val = int(match.group(1))
elif filt_function.strip() == "float":
extract_val = float(match.group(1))
elif filt_function.strip() == "str":
extract_val = str(match.group(1))
elif filt_function.strip() == "scientific":
try:
mult = {"m":1E-3, "u":1E-6, "n":1E-9,
"K":1E-3, "M":1E-6, "G":1E-9,}.get(match.group(2)[0], 1)
except:
mult = 1
extract_val = float(match.group(1))*mult
else:
extract_val = match.group(1)
except:
logger.exception("Filter failed")
extract_val= "Filter Failed"
resultDict[name] = extract_val
dummyparser = ConfigParser()
dummyparser.read_dict({"RESULTS": resultDict})
with open(r_filename+'.result', 'w') as configfile:
dummyparser.write(configfile)
logger.info("%s result extracted in file %s" %
(parse_section,r_filename+'.result'))
def run_rewrite_verilog():
# Rewrite the verilog after optimization
script_cmd = [
"read_blif %s" % args.top_module+".blif",
"write_verilog %s" % args.top_module+"_output_verilog.v"
]
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
try:
with open('yosys_rewrite_veri_output.txt', 'w+') as output:
process = subprocess.run(command,
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
if process.returncode:
logger.info("Rewrite veri yosys run failed with returncode %d",
process.returncode)
except:
logger.exception("Failed to run VPR")
clean_up_and_exit("")
logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt")
def run_netlists_verification():
compiled_file = "compiled_"+args.top_module
# include_netlists = args.top_module+"_include_netlists.v"
tb_top_formal = args.top_module+"_top_formal_verification_random_tb"
tb_top_autochecked = args.top_module+"_autocheck_top_tb"
# netlists_path = args.vpr_fpga_verilog_dir_val+"/SRC/"
command = [cad_tools["iverilog_path"]]
command += ["-o", compiled_file]
command += ["./SRC/%s_include_netlists.v" %
args.top_module]
command += ["-s"]
if args.vpr_fpga_verilog_formal_verification_top_netlist:
command += [tb_top_formal]
else:
command += [tb_top_autochecked]
run_command("iverilog_verification", "iverilog_output.txt", command)
vvp_command = ["vvp", compiled_file]
output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
if "Succeed" in output:
logger.info("VVP Simulation Successful")
else:
logger.info(str(output).split("\n")[-1])
def run_command(taskname, logfile, command, exit_if_fail=True):
try:
with open(logfile, 'w+') as output:
output.write(" ".join(command)+"\n")
process = subprocess.run(command,
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
if process.returncode:
logger.error("%s run failed with returncode %d" %
(taskname, process.returncode))
except (Exception, subprocess.CalledProcessError) as e:
logger.exception("failed to execute %s" % taskname)
process_failed_vpr_run(e.output)
if exit_if_fail:
clean_up_and_exit("Failed to run %s task" % taskname)
return None
logger.info("%s is written in file %s" % (taskname, logfile))
return process.stdout
def process_failed_vpr_run(vpr_output):
for line in vpr_output.split("\n"):
if "error" in line.lower():
logger.error("-->>" + line)
if __name__ == "__main__":
# Setting up print and logging system
logging.basicConfig(level=logging.INFO, stream=sys.stdout,
format='%(levelname)s - %(message)s')
logger = logging.getLogger('OpenFPGA_Flow_Logs')
# Parse commandline argument
args = parser.parse_args()
main()

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[GENERAL CONFIGURATION]
task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks
misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc
script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py

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import os
import sys
import shutil
import time
import shlex
import argparse
from configparser import ConfigParser, ExtendedInterpolation
import logging
import glob
import subprocess
import threading
import csv
from string import Template
import run_fpga_flow
import pprint
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configure logging system
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
logging.basicConfig(level=logging.INFO, stream=sys.stdout,
format='%(levelname)s (%(threadName)-9s) - %(message)s')
logger = logging.getLogger('OpenFPGA_Task_logs')
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Read commandline arguments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
parser = argparse.ArgumentParser()
parser.add_argument('tasks', nargs='+')
parser.add_argument('--maxthreads', type=int, default=2,
help="Number of fpga_flow threads to run default = 2," +
"Typically <= Number of processors on the system")
parser.add_argument('--config', help="Override default configuration")
parser.add_argument('--test_run', action="store_true",
help="Dummy run shows final generated VPR commands")
args = parser.parse_args()
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Read script configuration file
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
task_script_dir = os.path.dirname(os.path.abspath(__file__))
script_env_vars = ({"PATH": {
"OPENFPGA_FLOW_PATH": task_script_dir,
"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
os.pardir))}})
config = ConfigParser(interpolation=ExtendedInterpolation())
config.read_dict(script_env_vars)
config.read_file(open(os.path.join(task_script_dir, 'run_fpga_task.conf')))
gc = config["GENERAL CONFIGURATION"]
def main():
validate_command_line_arguments()
for eachtask in args.tasks:
logger.info("Currently running task %s" % eachtask)
eachtask = eachtask.replace("\\", "/").split("/")
job_run_list = generate_each_task_actions(eachtask)
eachtask = "_".join(eachtask)
if not args.test_run:
run_actions(job_run_list)
collect_results(job_run_list)
else:
pprint.pprint(job_run_list)
logger.info("Task execution completed")
exit()
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Subroutines starts here
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
def clean_up_and_exit(msg):
logger.error(msg)
logger.error("Existing . . . . . .")
exit()
def validate_command_line_arguments():
pass
def generate_each_task_actions(taskname):
"""
This script generates all the scripts required for each benchmark
"""
# Check if task directory exists and consistent
curr_task_dir = os.path.join(gc["task_dir"], *(taskname))
if not os.path.isdir(curr_task_dir):
clean_up_and_exit("Task directory [%s] not found" % curr_task_dir)
os.chdir(curr_task_dir)
curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf")
if not os.path.isfile(curr_task_conf_file):
clean_up_and_exit(
"Missing configuration file for task %s" % curr_task_dir)
# Create run directory for current task run ./runxxx
run_dirs = [int(os.path.basename(x)[-3:]) for x in glob.glob('run*[0-9]')]
curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1)
try:
os.mkdir(curr_run_dir)
if os.path.islink('latest'):
os.unlink("latest")
os.symlink(curr_run_dir, "latest")
logger.info('Created "%s" directory for current task run' %
curr_run_dir)
except:
logger.exception("")
logger.error("Failed to create new run directory in task directory")
os.chdir(curr_run_dir)
# Read task configuration file and check consistency
task_conf = ConfigParser(allow_no_value=True,
interpolation=ExtendedInterpolation())
task_conf.read_dict(script_env_vars)
task_conf.read_file(open(curr_task_conf_file))
required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"]
missing_section = list(set(required_sec)-set(task_conf.sections()))
if missing_section:
clean_up_and_exit("Missing sections %s" % " ".join(missing_section) +
" in task configuration file")
# Check if specified architecture files exist
archfile_list = []
for _, arch_file in task_conf["ARCHITECTURES"].items():
arch_full_path = arch_file
if os.path.isfile(arch_full_path):
archfile_list.append(arch_full_path)
else:
clean_up_and_exit("Architecture file not found: " +
"%s " % arch_file)
# Check if specified benchmark files exist
benchmark_list = []
for bech_name, each_benchmark in task_conf["BENCHMARKS"].items():
bench_files = []
for eachpath in each_benchmark.split(","):
files = glob.glob(eachpath)
if not len(files):
clean_up_and_exit(("No files added benchmark %s" % bech_name) +
" with path %s " % (eachpath))
bench_files += files
ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common")
benchmark_list.append({
"files": bench_files,
"top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top",
fallback="top"),
"ys_script": task_conf.get("SYNTHESIS_PARAM", bech_name+"_yosys",
fallback=ys_for_task),
})
# Create OpenFPGA flow run commnad for each combination of
# architecture, benchmark and parameters
# Create run_job object [arch, bench, run_dir, commnad]
flow_run_cmd_list = []
for indx, arch in enumerate(archfile_list):
for bench in benchmark_list:
flow_run_dir = get_flow_rundir(arch, bench["top_module"])
cmd = create_run_command(
flow_run_dir, arch, bench, task_conf)
flow_run_cmd_list.append({
"arch": arch,
"bench": bench,
"name": "%s_arch%d" % (bench["top_module"], indx),
"run_dir": flow_run_dir,
"commands": cmd,
"status": False})
return flow_run_cmd_list
def get_flow_rundir(arch, top_module, flow_params=None):
path = [
os.path.basename(arch).replace(".xml", ""),
top_module,
flow_params if flow_params else "common"
]
return os.path.abspath(os.path.join(*path))
def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf):
"""
Create_run_script function accepts run directory, architecture list and
fpga_flow configuration file and prepare final executable fpga_flow script
TODO : Replace this section after convert fpga_flow to python script
Config file creation and bechnmark list can be skipped
"""
# = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = =
if not os.path.isdir(gc["misc_dir"]):
clean_up_and_exit("Miscellaneous directory does not exist")
fpga_flow_script = os.path.join(gc["misc_dir"], "fpga_flow_template.sh")
if not os.path.isfile(fpga_flow_script):
clean_up_and_exit("Missing fpga_flow script template %s" %
fpga_flow_script)
fpga_flow_conf_tmpl = os.path.join(gc["misc_dir"], "fpga_flow_script.conf")
if not os.path.isfile(fpga_flow_conf_tmpl):
clean_up_and_exit("fpga_flow configuration tempalte is missing %s" %
fpga_flow_conf_tmpl)
# = = = = = = = = = = = = Create execution folder = = = = = = = = = = = =
if os.path.isdir(curr_job_dir):
question = "One the result directory already exist.\n"
question += "%s\n" % curr_job_dir
reply = str(input(question+' (y/n): ')).lower().strip()
if reply[:1] in ['y', 'yes']:
shutil.rmtree(curr_job_dir)
else:
logger.info("Result directory removal denied by the user")
exit()
os.makedirs(curr_job_dir)
# Make execution command to run Open FPGA flow
command = [archfile] + benchmark_obj["files"]
command += ["--top_module", benchmark_obj["top_module"]]
command += ["--run_dir", curr_job_dir]
if task_conf.getboolean("GENERAL", "power_analysis", fallback=False):
command += ["--power"]
command += ["--power_tech",
task_conf.get("GENERAL", "power_tech_file")]
if task_conf.getboolean("GENERAL", "spice_output", fallback=False):
command += ["--vpr_fpga_spice"]
if task_conf.getboolean("GENERAL", "verilog_output", fallback=False):
command += ["--vpr_fpga_verilog"]
# Add other paramters to pass
for key, values in task_conf["SCRIPT_PARAM"].items():
command += ["--"+key, values]
return command
def run_single_script(s, eachJob):
logger.debug('Added job in pool')
with s:
logger.debug("Running OpenFPGA flow with " +
" ".join(eachJob["commands"]))
name = threading.currentThread().getName()
try:
logfile = "%s_out.log" % name
with open(logfile, 'w+') as output:
process = subprocess.run(["python3.5",
gc["script_default"]] +
eachJob["commands"],
check=True,
stdout=subprocess.PIPE,
stderr=subprocess.PIPE,
universal_newlines=True)
output.write(process.stdout)
eachJob["status"] = True
except:
logger.error("Failed to execute openfpga flow - " +
eachJob["name"])
# logger.exception("Failed to launch openfpga flow")
logger.info("%s Finished " % name)
def run_actions(job_run_list):
thread_sema = threading.Semaphore(args.maxthreads)
thred_list = []
for index, eachjob in enumerate(job_run_list):
t = threading.Thread(target=run_single_script,
name='Job_%02d' % (index+1),
args=(thread_sema, eachjob))
t.start()
thred_list.append(t)
for eachthread in thred_list:
eachthread.join()
def collect_results(job_run_list):
task_result = []
for run in job_run_list:
if not run["status"]:
continue
# Check if any result file exist
if not glob.glob(os.path.join(run["run_dir"], "*.result")):
logger.info("No result files found for %s" % run["name"])
# Read and merge result file
vpr_res = ConfigParser(allow_no_value=True,
interpolation=ExtendedInterpolation())
vpr_res.read_file(
open(os.path.join(run["run_dir"], "vpr_stat.result")))
result = dict(vpr_res["RESULTS"])
result["name"] = run["name"]
task_result.append(result)
if len(task_result):
with open("task_result.csv", 'w', newline='') as csvfile:
writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys())
writer.writeheader()
for eachResult in task_result:
writer.writerow(eachResult)
if __name__ == "__main__":
main()

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**/run[0-9][0-9][0-9]
**/latest

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openfpga_flow/tasks/basic_flow/config/golden_results.txt Normal file
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arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem
k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1

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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml
power_analysis = true
spice_output=false
verilog_output=false
timeout_each_job = 20*60
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys
bench0_top = s298
bench1_top = alu4
bench2_top = s38417
bench0_yosys=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys
[SCRIPT_PARAM]
min_route_chan_width=30
[POST_RUN]
# Not Implemented yet
# Parse info and how to parse
parse_file=vpr_standard.txt
# Pass requirements
pass_requirements_file=pass_requirements.txt

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XSym
0006
de6ba653dd63797278d7fa829999bf6c
run003

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openfpga_flow/tech/PTM_130nm/130nm.pm Normal file
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* Beta Version released on 2/22/06
* PTM 130nm NMOS
.model nmos nmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 2.25e-9 toxp = 1.6e-9 toxm = 2.25e-9
+dtox = 0.65e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 2.25e-9
+xl = -60e-9
+vth0 = 0.3782 k1 = 0.4 k2 = 0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.2e-010
+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 3.92e-008
+ngate = 2e+020 ndep = 1.54e+018 nsd = 2e+020 phin = 0
+cdsc = 0.0002 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.13 nfactor = 1.5 eta0 = 0.0092 etab = 0
+vfb = -0.55 u0 = 0.05928 ua = 6e-010 ub = 1.2e-018
+uc = 0 vsat = 100370 a0 = 1 ags = 1e-020
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.06
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rdsw = 200 rsw = 100 rdw = 100
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028
+cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
* PTM 130nm PMOS
.model pmos pmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 2.35e-009 toxp = 1.6e-009 toxm = 2.35e-009
+dtox = 0.75e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 2.35e-009
+xl = -60e-9
+vth0 = -0.321 k1 = 0.4 k2 = -0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009
+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 3.92e-008
+ngate = 2e+020 ndep = 1.14e+018 nsd = 2e+020 phin = 0
+cdsc = 0.000258 cdscb = 0 cdscd = 6.1e-008 cit = 0
+voff = -0.126 nfactor = 1.5 eta0 = 0.0092 etab = 0
+vfb = 0.55 u0 = 0.00835 ua = 2.0e-009 ub = 0.5e-018
+uc = -3e-011 vsat = 70000 a0 = 1.0 ags = 1e-020
+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0
+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rdsw = 240 rsw = 120 rdw = 120
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012
+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

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openfpga_flow/tech/PTM_130nm/readme.txt Normal file
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This technology file was generated using the Nano-CMOS tool from http://ptm.asu.edu/
The following default parameters were used:
NMOS
Leff=49 nm 10%
Vth=0.18 V 30mV
Vdd=1.3 V
Tox=1.6 nm
Rdsw=200 Ohm
PMOS
Leff=49 nm 10%
Vth=-0.18 V 30mV
Vdd=1.3 V
Tox=1.6 nm
Rdsw=240 Ohm

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openfpga_flow/tech/PTM_22nm/22nm.pm Normal file
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* PTM High Performance 22nm Metal Gate / High-K / Strained-Si
* nominal Vdd = 0.8V
.model nmos nmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 1.05e-009 toxp = 8e-010 toxm = 1.05e-009
+dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 1.05e-009
+xl = -9e-9
+vth0 = 0.50308 k1 = 0.4 k2 = 0 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011
+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 7.2e-009
+ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0
+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.13 nfactor = 2.3 eta0 = 0.004 etab = 0
+vfb = -0.55 u0 = 0.04 ua = 6e-010 ub = 1.2e-018
+uc = 0 vsat = 250000 a0 = 1 ags = 0
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000
+rsh = 5 rdsw = 145 rsw = 75 rdw = 75
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889
+cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010
+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0
+dwj = 0 xgw = 0 xgl = 0
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
.model pmos pmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 1.1e-009 toxp = 8e-010 toxm = 1.1e-009
+dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 1.1e-009
+xl = -9e-9
+vth0 = -0.4606 k1 = 0.4 k2 = -0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011
+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 7.2e-009
+ngate = 1e+023 ndep = 4.4e+018 nsd = 2e+020 phin = 0
+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.126 nfactor = 2.1 eta0 = 0.0038 etab = 0
+vfb = 0.55 u0 = 0.0095 ua = 2e-009 ub = 5e-019
+uc = 0 vsat = 210000 a0 = 1 ags = 1e-020
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000
+rsh = 5 rdsw = 145 rsw = 72.5 rdw = 72.5
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889
+cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010
+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0
+dwj = 0 xgw = 0 xgl = 0
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

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This technology file was obtained here:
http://ptm.asu.edu/modelcard/LP/22nm_LP.pm

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* PTM High Performance 45nm Metal Gate / High-K / Strained-Si
* nominal Vdd = 1.0V
.model nmos nmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 1.25e-009 toxp = 1e-009 toxm = 1.25e-009
+dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 3.75e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 1.25e-009
+xl = -20e-9
+vth0 = 0.46893 k1 = 0.4 k2 = 0 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010
+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 1.4e-008
+ngate = 1e+023 ndep = 3.24e+018 nsd = 2e+020 phin = 0
+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.13 nfactor = 2.22 eta0 = 0.0055 etab = 0
+vfb = -0.55 u0 = 0.054 ua = 6e-010 ub = 1.2e-018
+uc = 0 vsat = 170000 a0 = 1 ags = 0
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000
+rsh = 5 rdsw = 155 rsw = 80 rdw = 80
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0025
+cigc = 0.002 aigsd = 0.02 bigsd = 0.0025 cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010
+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0
+dwj = 0 xgw = 0 xgl = 0
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
.model pmos pmos level = 54
+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 1.3e-009 toxp = 1e-009 toxm = 1.3e-009
+dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 3.75e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 1.3e-009
+xl = -20e-9
+vth0 = -0.49158 k1 = 0.4 k2 = -0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011
+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008
+ngate = 1e+023 ndep = 2.44e+018 nsd = 2e+020 phin = 0
+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.126 nfactor = 2.1 eta0 = 0.0055 etab = 0
+vfb = 0.55 u0 = 0.02 ua = 2e-009 ub = 5e-019
+uc = 0 vsat = 150000 a0 = 1 ags = 1e-020
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000
+rsh = 5 rdsw = 155 rsw = 75 rdw = 75
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.010687 bigc = 0.0012607
+cigc = 0.0008 aigsd = 0.010687 bigsd = 0.0012607 cigsd = 0.0008
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010
+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0
+dwj = 0 xgw = 0 xgl = 0
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

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This technology file was generated using the Nano-CMOS tool from http://ptm.asu.edu/
The following default parameters were used:
NMOS
Leff=17.5 nm 10%
Vth=0.18 V 30mV
Vdd=1 V
Tox=1.1 nm
Rdsw=155 Ohm
PMOS
Leff=17.5 nm 10%
Vth=-0.18 V 30mV
Vdd=1 V
Tox=1.1 nm
Rdsw=155 Ohm

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run_local.bat
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docker run -it --rm -v $PWD:/localfile -w="/localfile/vpr7_x2p/vpr" open_fpga bash
docker run -it --rm -v "%cd%":/localfile/OpenFPGA -w="/localfile/OpenFPGA" goreganesh/open_fpga bash
pause

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run_local.sh Executable file
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#!/bin/bash
docker run -it --rm -v "${PWD}":/root/dev/OpenFPGA -w="/root/dev/OpenFPGA" goreganesh/open_fpga bash
pause

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run_test.sh Normal file
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
--top_module s298 \
--power \
--power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \
--end_flow_with_test \
--vpr_fpga_verilog_include_icarus_simulator \
--vpr_fpga_verilog_formal_verification_top_netlist \
--vpr_fpga_verilog_include_timing \
--vpr_fpga_verilog_include_signal_init \
--vpr_fpga_verilog_print_autocheck_top_testbench

33
vpr7_x2p/vpr/go_ganesh.sh
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@ -1,33 +0,0 @@
#!/bin/bash
echo "#################################################"
echo "The current shell environment is the following:"
echo $0
echo "#################################################"
# Example of how to run vprset circuit_name = pip_add
#set circuit_name = pip_add
circuit_name=sync_4bits_add
circuit_blif=${PWD}/Circuits/${circuit_name}.blif
arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml
circuit_act=${PWD}/Circuits/${circuit_name}.act
circuit_verilog=${PWD}/Circuits/${circuit_name}.v
spice_output=${PWD}/spice_demo
verilog_output=${PWD}/verilog_demo
modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
openfpga_path=${PWD}/../..
# Make sure a clean start
rm -rf ${spice_output}
rm -rf ${verilog_output}
echo "*******************************"
echo "THIS SCRIPT NEEDS TO BE SOURCED"
echo "source ./go.sh"
echo "*******************************"
sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file}
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench