plug in module manager

2019-08-23 17:39:29 -06:00 · 2019-08-23 17:39:29 -06:00 · 056c45321b
parent 8fc258cc93
commit 056c45321b
1 changed files with 1 additions and 1 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
@ -120,7 +120,7 @@ void print_verilog_module_declaration(std::fstream& fp,
  check_file_handler(fp);

  print_verilog_module_definition(fp, module_manager.module_name(module_id));
-  
+
  print_verilog_module_ports(fp, module_manager, module_id);

  fp << std::endl << ");" << std::endl;