From 056c45321bed08aa161ed795bc7a88fe4e5c36c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 17:39:29 -0600 Subject: [PATCH] plug in module manager --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index f58ee587e..eab5e1b53 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -120,7 +120,7 @@ void print_verilog_module_declaration(std::fstream& fp, check_file_handler(fp); print_verilog_module_definition(fp, module_manager.module_name(module_id)); - + print_verilog_module_ports(fp, module_manager, module_id); fp << std::endl << ");" << std::endl;