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Explicit verilog passing all tests

This commit is contained in:
Baudouin Chauviere 2019-10-02 10:22:28 -06:00
parent 6b3e1fd410
commit 01ff484158
3 changed files with 1074 additions and 489 deletions
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1542
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
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File diff suppressed because it is too large Load Diff

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -1215,6 +1215,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
FILE* fp,
bool is_explicit_mapping) {
int num_mem_bits = 0;
t_spice_model* ccff_mem_model = NULL;
/* Check */
assert(SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type);
@ -1226,6 +1227,9 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
/* Get the total memory bits */
num_mem_bits = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
/* Get model of the configuration chain */
get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model);
/* Dump each Scan-chain FF */
fprintf(fp, "//------ Configuration peripheral for Scan-chain FFs -----\n");
fprintf(fp, "%s %s_0_ (\n",
@ -1243,7 +1247,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".ccff_ccff_in_local_bus (");
fprintf(fp, ".%s_ccff_in_local_bus (",
ccff_mem_model->prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
@ -1251,7 +1256,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".ccff_ccff_out_local_bus (");
fprintf(fp, ".%s_ccff_out_local_bus (",
ccff_mem_model->prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {

11
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -1560,6 +1560,7 @@ void dump_verilog_sram_local_ports(FILE* fp,
t_spice_model_port** blb_port = NULL;
t_spice_model_port** wlb_port = NULL;
t_spice_model* cur_sram_verilog_model = NULL;
t_spice_model* ccff_mem_model = NULL;
/* Check the file handler*/
if (NULL == fp) {
@ -1577,6 +1578,10 @@ void dump_verilog_sram_local_ports(FILE* fp,
__FILE__, __LINE__, sram_lsb, sram_msb);
return;
}
/* Get model of the configuration chain */
get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model);
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
case SPICE_SRAM_MEMORY_BANK:
@ -1593,7 +1598,8 @@ void dump_verilog_sram_local_ports(FILE* fp,
case SPICE_SRAM_SCAN_CHAIN:
/* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".ccff_ccff_head(");
fprintf(fp, ".%s_ccff_head(",
ccff_mem_model->prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_lsb, sram_lsb,
@ -1604,7 +1610,8 @@ void dump_verilog_sram_local_ports(FILE* fp,
fprintf(fp, ",\n");
/* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */
if (true == is_explicit_mapping) {
fprintf(fp, ".ccff_ccff_tail(");
fprintf(fp, ".%s_ccff_tail(",
ccff_mem_model->prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
sram_msb, sram_msb,