Merge remote-tracking branch 'origin/ganesh_dev' into dev
This commit is contained in:
Ganesh Gore
commit
ec3854a648
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@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --exit_on_fail
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
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end_section "OpenFPGA.TaskTun"
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@ -0,0 +1,8 @@
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read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} }
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set_top r:${SOURCE_TOP_DIR}
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read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} }
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set_top i:${IMPL_TOP_DIR}
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match
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${MATCH_MODUEL_LIST}
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verify
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@ -36,7 +36,7 @@ if sys.version_info[0] < 3:
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# Configure logging system
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)10s) - %(message)s')
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format='%(levelname)s (%(threadName)15s) - %(message)s')
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logger = logging.getLogger('OpenFPGA_Task_logs')
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@ -53,9 +53,9 @@ parser.add_argument('--test_run', action="store_true",
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help="Dummy run shows final generated VPR commands")
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parser.add_argument('--debug', action="store_true",
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help="Run script in debug mode")
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parser.add_argument('--exit_on_fail', action="store_true",
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parser.add_argument('--continue_on_fail', action="store_true",
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help="Exit script with return code")
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parser.add_argument('--skip_thread_logs', action="store_true",
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parser.add_argument('--show_thread_logs', action="store_true",
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help="Skips logs from running thread")
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args = parser.parse_args()
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@ -252,7 +252,7 @@ def generate_each_task_actions(taskname):
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flow_run_cmd_list.append({
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"arch": arch,
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"bench": bench,
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"name": "%02d_arch%s_%s" % (indx, bench["top_module"], lbl),
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"name": "%02d_%s_%s" % (indx, bench["top_module"], lbl),
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"run_dir": flow_run_dir,
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"commands": command,
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"finished" : False,
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@ -345,14 +345,11 @@ def strip_child_logger_info(line):
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def run_single_script(s, eachJob, job_list):
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logger.debug('Added job in pool')
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with s:
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logger.debug("Running OpenFPGA flow with " +
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" ".join(eachJob["commands"]))
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name = threading.currentThread().getName()
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thread_name = threading.currentThread().getName()
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eachJob["starttime"] = time.time()
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try:
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logfile = "%s_out.log" % name
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logfile = "%s_out.log" % thread_name
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with open(logfile, 'w+') as output:
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output.write("* "*20 + '\n')
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output.write("RunDirectory : %s\n" % os.getcwd())
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@ -360,30 +357,31 @@ def run_single_script(s, eachJob, job_list):
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eachJob["commands"]
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output.write(" ".join(command) + '\n')
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output.write("* "*20 + '\n')
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logger.debug("Running OpenFPGA flow with [%s]" % command)
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process = subprocess.Popen(command,
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stdout=subprocess.PIPE,
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stderr=subprocess.STDOUT,
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universal_newlines=True)
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for line in process.stdout:
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if not args.skip_thread_logs:
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if args.show_thread_logs:
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strip_child_logger_info(line[:-1])
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sys.stdout.buffer.flush()
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output.write(line)
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process.wait()
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if process.returncode:
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raise subprocess.CalledProcessError(0, command)
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raise subprocess.CalledProcessError(0, " ".join(command))
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eachJob["status"] = True
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except:
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logger.exception("Failed to execute openfpga flow - " +
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eachJob["name"])
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if args.exit_on_fail:
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clean_up_and_exit("Faile to run task %s exiting" % name)
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if not args.continue_on_fail:
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os._exit(1)
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eachJob["endtime"] = time.time()
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timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"]))
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timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \
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else str(timediff)
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logger.info("%s Finished with returncode %d, Time Taken %s " %
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(name, process.returncode, timestr))
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(thread_name, process.returncode, timestr))
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eachJob["finished"] = True
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no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list])
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logger.info("***** %d runs pending *****" % (no_of_finished_job))
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@ -391,15 +389,13 @@ def run_single_script(s, eachJob, job_list):
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def run_actions(job_list):
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thread_sema = threading.Semaphore(args.maxthreads)
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thred_list = []
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for index, eachjob in enumerate(job_list):
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JobID = 'Job_%02d' % (index+1)
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logger.info("Running %s = %s" % (JobID, eachjob["name"]))
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t = threading.Thread(target=run_single_script,
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name=JobID, args=(thread_sema, eachjob, job_list))
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thread_list = []
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for _ , eachjob in enumerate(job_list):
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t = threading.Thread(target=run_single_script, name=eachjob["name"],
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args=(thread_sema, eachjob, job_list))
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t.start()
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thred_list.append(t)
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for eachthread in thred_list:
|
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thread_list.append(t)
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for eachthread in thread_list:
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eachthread.join()
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|
||||
|
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|
|
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|
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@ -0,0 +1,86 @@
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from string import Template
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import sys
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import os
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import argparse
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import subprocess
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import logging
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from pprint import pprint
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|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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||||
# Configure logging system
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)10s) - %(message)s')
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||||
logger = logging.getLogger('Modelsim_run_log')
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|
||||
parser = argparse.ArgumentParser()
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parser.add_argument('files', nargs='+')
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||||
parser.add_argument('--modelsim_template', type=str,
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help="Modelsim verification template file")
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||||
parser.add_argument('--run_sim', action="store_true",
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help="Execute generated script in formality")
|
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args = parser.parse_args()
|
||||
|
||||
|
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if not args.modelsim_template:
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task_script_dir = os.path.dirname(os.path.abspath(__file__))
|
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args.modelsim_template = os.path.join(task_script_dir, os.pardir,
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"misc", "modelsim_template.j2")
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|
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args.modelsim_template = os.path.abspath(args.modelsim_template)
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||||
|
||||
|
||||
def main():
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for eachFile in args.files:
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eachFile = os.path.abspath(eachFile)
|
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directory = os.path.dirname(eachFile)
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os.chdir(directory)
|
||||
with open(eachFile, 'r') as fp:
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lines = fp.read().split("\n")
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SplitL = [indx for indx, eachL in enumerate(lines) if eachL == ""]
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SplitL = list(zip([0] + SplitL[:-1], SplitL))
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for indx, eachSection in enumerate(SplitL):
|
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SplitL[indx] = list(filter(None, lines[slice(*eachSection)]))
|
||||
|
||||
match_str = "set_user_match r:%s i:%s -type port -noninverted"
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lables = {"SOURCE_DESIGN": " ".join(SplitL[0]),
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"SOURCE_TOP_DIR": "/WORK/" + " ".join(SplitL[1]),
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"IMPL_DESIGN": " ".join(SplitL[2]),
|
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"IMPL_TOP_DIR": "/WORK/" + " ".join(SplitL[3]),
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||||
"MATCH_MODUEL_LIST": "\n".join([match_str % tuple(eachPort.split()) for eachPort in SplitL[4]])
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}
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||||
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tmpl = Template(open(args.modelsim_template, encoding='utf-8').read())
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with open("Output.tcl", 'w', encoding='utf-8') as tclout:
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tclout.write(tmpl.substitute(lables))
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if args.run_sim:
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formality_run_string = ["formality", "-file", "Output.tcl"]
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run_command("Modelsim run", "modelsim_run.log", formality_run_string)
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else:
|
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with open("Output.tcl", 'r', encoding='utf-8') as tclout:
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print(tclout.read())
|
||||
|
||||
|
||||
def run_command(taskname, logfile, command, exit_if_fail=True):
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logger.info("Launching %s " % taskname)
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||||
with open(logfile, 'w+') as output:
|
||||
try:
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||||
output.write(" ".join(command)+"\n")
|
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process = subprocess.run(command,
|
||||
check=True,
|
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stdout=subprocess.PIPE,
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||||
stderr=subprocess.PIPE,
|
||||
universal_newlines=True)
|
||||
output.write(process.stdout)
|
||||
if process.returncode:
|
||||
logger.error("%s run failed with returncode %d" %
|
||||
(taskname, process.returncode))
|
||||
except (Exception, subprocess.CalledProcessError) as e:
|
||||
logger.exception("failed to execute %s" % taskname)
|
||||
return None
|
||||
logger.info("%s is written in file %s" % (taskname, logfile))
|
||||
return process.stdout
|
||||
|
||||
|
||||
if __name__ == "__main__":
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main()
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||||
|
|
@ -39,203 +39,217 @@
|
|||
#include "verilog_routing.h"
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||||
#include "verilog_tcl_utils.h"
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||||
|
||||
|
||||
static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){
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int i, j;
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// char* tmp = NULL;
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||||
const t_pb_type *pb_type;
|
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t_mode *mode;
|
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t_pb_graph_node * node;
|
||||
// char* index = NULL;
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static void searching_used_latch(FILE *fp, t_pb *pb, int pb_index, char *chomped_circuit_name, char *inst_name)
|
||||
{
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int i, j;
|
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// char* tmp = NULL;
|
||||
const t_pb_type *pb_type;
|
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t_mode *mode;
|
||||
t_pb_graph_node *node;
|
||||
// char* index = NULL;
|
||||
|
||||
pb_type = pb->pb_graph_node->pb_type;
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node = pb->pb_graph_node->physical_pb_graph_node;
|
||||
mode = &pb_type->modes[pb->mode];
|
||||
pb_type = pb->pb_graph_node->pb_type;
|
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node = pb->pb_graph_node->physical_pb_graph_node;
|
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mode = &pb_type->modes[pb->mode];
|
||||
|
||||
// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index)))));
|
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// tmp = ff_hierarchy;
|
||||
// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_"));
|
||||
// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index)))));
|
||||
// tmp = ff_hierarchy;
|
||||
// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_"));
|
||||
|
||||
if (pb_type->num_modes > 0) {
|
||||
for (i = 0; i < mode->num_pb_type_children; i++) {
|
||||
for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
|
||||
// if(strcmp(pb_type->name, mode->name) != 0)
|
||||
// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index)));
|
||||
if(pb->child_pbs[i][j].name != NULL)
|
||||
searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
|
||||
}
|
||||
}
|
||||
} else if((pb_type->class_type == LATCH_CLASS) && (pb->name)){
|
||||
// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_"))));
|
||||
fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name,
|
||||
pb->name,
|
||||
inst_name,
|
||||
gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node) );
|
||||
}
|
||||
//free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp
|
||||
return;
|
||||
if (pb_type->num_modes > 0)
|
||||
{
|
||||
for (i = 0; i < mode->num_pb_type_children; i++)
|
||||
{
|
||||
for (j = 0; j < mode->pb_type_children[i].num_pb; j++)
|
||||
{
|
||||
// if(strcmp(pb_type->name, mode->name) != 0)
|
||||
// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index)));
|
||||
if (pb->child_pbs[i][j].name != NULL)
|
||||
searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((pb_type->class_type == LATCH_CLASS) && (pb->name))
|
||||
{
|
||||
// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_"))));
|
||||
fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name,
|
||||
pb->name,
|
||||
inst_name,
|
||||
gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node));
|
||||
}
|
||||
//free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp
|
||||
return;
|
||||
}
|
||||
|
||||
static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){
|
||||
t_pb* pb;
|
||||
char* inst_name = NULL;
|
||||
const t_pb_type *pb_type;
|
||||
t_mode *mode;
|
||||
int i, j, x_pos, y_pos;
|
||||
char* grid_x = NULL;
|
||||
char* grid_y = NULL;
|
||||
static void clb_iteration(FILE *fp, char *chomped_circuit_name, int h)
|
||||
{
|
||||
t_pb *pb;
|
||||
char *inst_name = NULL;
|
||||
const t_pb_type *pb_type;
|
||||
t_mode *mode;
|
||||
int i, j, x_pos, y_pos;
|
||||
char *grid_x = NULL;
|
||||
char *grid_y = NULL;
|
||||
|
||||
x_pos = block[h].x;
|
||||
y_pos = block[h].y;
|
||||
x_pos = block[h].x;
|
||||
y_pos = block[h].y;
|
||||
|
||||
pb = (t_pb*) block[h].pb;
|
||||
pb = (t_pb *)block[h].pb;
|
||||
|
||||
pb_type = pb->pb_graph_node->pb_type;
|
||||
mode = &pb_type->modes[pb->mode];
|
||||
pb_type = pb->pb_graph_node->pb_type;
|
||||
mode = &pb_type->modes[pb->mode];
|
||||
|
||||
grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_"));
|
||||
grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_"));
|
||||
grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_"));
|
||||
grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_"));
|
||||
|
||||
|
||||
if (strcmp(pb_type->name, FILL_TYPE->name) == 0) {
|
||||
inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid",my_strcat(grid_x, my_strcat(grid_y, "/" )))))));
|
||||
if (pb_type->num_modes > 0) {
|
||||
for (i = 0; i < mode->num_pb_type_children; i++) {
|
||||
inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_")))));
|
||||
for (j = 0; j < mode->pb_type_children[i].num_pb; j++) {
|
||||
/* If child pb is not used but routing is used, I must print things differently */
|
||||
if ((pb->child_pbs[i] != NULL)
|
||||
&& (pb->child_pbs[i][j].name != NULL)) {
|
||||
searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
if (strcmp(pb_type->name, FILL_TYPE->name) == 0)
|
||||
{
|
||||
inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid", my_strcat(grid_x, my_strcat(grid_y, "/")))))));
|
||||
if (pb_type->num_modes > 0)
|
||||
{
|
||||
for (i = 0; i < mode->num_pb_type_children; i++)
|
||||
{
|
||||
inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_")))));
|
||||
for (j = 0; j < mode->pb_type_children[i].num_pb; j++)
|
||||
{
|
||||
/* If child pb is not used but routing is used, I must print things differently */
|
||||
if ((pb->child_pbs[i] != NULL) && (pb->child_pbs[i][j].name != NULL))
|
||||
{
|
||||
searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void match_registers(FILE *fp, char* chomped_circuit_name) {
|
||||
int h;
|
||||
|
||||
for(h = 0; h < copy_nb_clusters; h++)
|
||||
clb_iteration(fp, chomped_circuit_name, h);
|
||||
/* for(h = 0; h < copy_nb_clusters; h++){
|
||||
free_cb(copy_clb[h].pb);
|
||||
free(copy_clb[h].name);
|
||||
free(copy_clb[h].nets);
|
||||
free(copy_clb[h].pb);
|
||||
}*/
|
||||
// free(copy_clb);
|
||||
// free(block);
|
||||
return;
|
||||
}
|
||||
|
||||
static
|
||||
void formality_include_user_defined_verilog_netlists(FILE* fp,
|
||||
t_spice spice) {
|
||||
static void formality_include_user_defined_verilog_netlists(FILE *fp,
|
||||
t_spice spice)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* A valid file handler*/
|
||||
if (NULL == fp) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d])Invalid File Handler!\n",
|
||||
if (NULL == fp)
|
||||
{
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d])Invalid File Handler!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Include user-defined sub-circuit netlist */
|
||||
for (i = 0; i < spice.num_include_netlist; i++) {
|
||||
if (0 == spice.include_netlists[i].included) {
|
||||
for (i = 0; i < spice.num_include_netlist; i++)
|
||||
{
|
||||
if (0 == spice.include_netlists[i].included)
|
||||
{
|
||||
assert(NULL != spice.include_netlists[i].path);
|
||||
fprintf(fp, "%s ", spice.include_netlists[i].path);
|
||||
fprintf(fp, "%s \n", spice.include_netlists[i].path);
|
||||
spice.include_netlists[i].included = 1;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(1 == spice.include_netlists[i].included);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void write_formality_script (t_syn_verilog_opts fpga_verilog_opts,
|
||||
char* fm_dir_formatted,
|
||||
char* src_dir_formatted,
|
||||
char* chomped_circuit_name,
|
||||
t_spice spice){
|
||||
int iblock;
|
||||
char* formality_script_file_name = NULL;
|
||||
char* benchmark_path = NULL;
|
||||
char* original_output_name = NULL;
|
||||
/* int output_length; */
|
||||
/* int pos; */
|
||||
FILE* fp = NULL;
|
||||
void write_formality_script(t_syn_verilog_opts fpga_verilog_opts,
|
||||
char *fm_dir_formatted,
|
||||
char *src_dir_formatted,
|
||||
char *chomped_circuit_name,
|
||||
t_spice spice)
|
||||
{
|
||||
int iblock, h;
|
||||
char *formScriptfp = NULL;
|
||||
char *benchmark_path = NULL;
|
||||
char *original_output_name = NULL;
|
||||
/* int output_length; */
|
||||
/* int pos; */
|
||||
FILE *fp = NULL;
|
||||
|
||||
if(TRUE == fpga_verilog_opts.print_autocheck_top_testbench){
|
||||
if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench)
|
||||
{
|
||||
benchmark_path = fpga_verilog_opts.reference_verilog_benchmark_file;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
benchmark_path = "Insert verilog benchmark path";
|
||||
}
|
||||
|
||||
formality_script_file_name = my_strcat(fm_dir_formatted, my_strcat(chomped_circuit_name, formality_script_name_postfix));
|
||||
fp = fopen(formality_script_file_name, "w");
|
||||
if (NULL == fp) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(FILE:%s,LINE[%d])Failure in create formality script %s",
|
||||
__FILE__, __LINE__, formality_script_file_name);
|
||||
exit(1);
|
||||
}
|
||||
formScriptfp = my_strcat(fm_dir_formatted,
|
||||
my_strcat(chomped_circuit_name,
|
||||
formality_script_name_postfix));
|
||||
fp = fopen(formScriptfp, "w");
|
||||
if (NULL == fp)
|
||||
{
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(FILE:%s,LINE[%d])Failure in create formality script %s",
|
||||
__FILE__, __LINE__, formScriptfp);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Load Verilog benchmark as reference */
|
||||
fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path);
|
||||
fprintf(fp, "%s\n\n", benchmark_path);
|
||||
|
||||
/* Set reference top */
|
||||
fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name);
|
||||
fprintf(fp, "%s\n\n", chomped_circuit_name);
|
||||
|
||||
/* Load generated verilog as implemnetation */
|
||||
fprintf(fp, "read_verilog -container i -libname WORK -05 { ");
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
chomped_circuit_name,
|
||||
verilog_top_postfix);
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
chomped_circuit_name,
|
||||
formal_verification_verilog_file_postfix);
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted, chomped_circuit_name,
|
||||
verilog_top_postfix);
|
||||
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
chomped_circuit_name,
|
||||
formal_verification_verilog_file_postfix);
|
||||
|
||||
init_include_user_defined_verilog_netlists(spice);
|
||||
formality_include_user_defined_verilog_netlists(fp, spice);
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
default_rr_dir_name,
|
||||
routing_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
default_lb_dir_name,
|
||||
logic_block_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s ", src_dir_formatted,
|
||||
default_submodule_dir_name,
|
||||
submodule_verilog_file_name);
|
||||
fprintf(fp, "}\n");
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_rr_dir_name,
|
||||
routing_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_lb_dir_name,
|
||||
logic_block_verilog_file_name);
|
||||
fprintf(fp, "%s%s%s\n", src_dir_formatted,
|
||||
default_submodule_dir_name,
|
||||
submodule_verilog_file_name);
|
||||
fprintf(fp, "\n");
|
||||
|
||||
/* Set implementation top */
|
||||
fprintf(fp, "set_top i:/WORK/%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix));
|
||||
fprintf(fp, "%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix));
|
||||
/* Run matching */
|
||||
fprintf(fp, "match\n");
|
||||
fprintf(fp, "\n");
|
||||
/* Add manual matching for the outputs */
|
||||
for (iblock = 0; iblock < num_logical_blocks; iblock++) {
|
||||
for (iblock = 0; iblock < num_logical_blocks; iblock++)
|
||||
{
|
||||
original_output_name = NULL;
|
||||
if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) {
|
||||
if (iopad_verilog_model == logical_block[iblock].mapped_spice_model)
|
||||
{
|
||||
/* Make sure We find the correct logical block !*/
|
||||
assert((VPACK_INPAD == logical_block[iblock].type)
|
||||
||(VPACK_OUTPAD == logical_block[iblock].type));
|
||||
if(VPACK_OUTPAD == logical_block[iblock].type){
|
||||
assert((VPACK_INPAD == logical_block[iblock].type) || (VPACK_OUTPAD == logical_block[iblock].type));
|
||||
if (VPACK_OUTPAD == logical_block[iblock].type)
|
||||
{
|
||||
/* output_length = strlen(logical_block[iblock].name); */
|
||||
original_output_name = logical_block[iblock].name + 4;
|
||||
/* printf("%s", original_output_name); */
|
||||
fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n",
|
||||
// fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n",
|
||||
fprintf(fp, "/WORK/%s/%s /WORK/%s/%s[0]\n",
|
||||
chomped_circuit_name,
|
||||
original_output_name,
|
||||
original_output_name,
|
||||
my_strcat(chomped_circuit_name, formal_verification_top_postfix),
|
||||
my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix));
|
||||
my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix));
|
||||
}
|
||||
}
|
||||
}
|
||||
match_registers(fp, chomped_circuit_name);
|
||||
|
||||
for (h = 0; h < copy_nb_clusters; h++)
|
||||
clb_iteration(fp, chomped_circuit_name, h);
|
||||
|
||||
/* Run verification */
|
||||
fprintf(fp, "verify\n");
|
||||
fprintf(fp, "\n");
|
||||
/* Script END */
|
||||
fclose(fp);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue